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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1999 may 11 integrated circuits SAA6721e sxga rgb to tft graphics engine
1999 may 11 2 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e contents 1 features 1.1 rgb video input 1.2 yuv video input 1.3 video processing 1.4 on screen display 1.5 video output 1.6 memory interface 1.7 miscellaneous 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning information 7 functional description 7.1 data path 7.2 system clocks 7.2.1 input interface clock (vclk) 7.2.2 memory interface clock (mclki) 7.2.3 i 2 c-bus interface clock (scl) 7.2.4 system clock (clk) 7.2.5 tft panel clock (pclk) 7.3 rgb input port 7.4 yuv input port 7.5 tft output port 7.5.1 single pixel mode 7.5.2 double pixel mode 7.6 memory port 7.6.1 sdram memory configuration 7.6.2 sgram memory configuration 7.7 i 2 c-bus interface 7.8 de-interlacing algorithms 7.8.1 static mesh mode 7.8.2 spatial filtering 7.8.3 temporal filtering 7.9 scaling algorithm 7.9.1 upscaling 7.9.2 downscaling 8 system description 8.1 programming registers 8.2 clock management 8.2.1 clock generation and multiplexing 8.2.2 clock divider 8.3 rgb/yuv input interface 8.3.1 sampling mode 8.3.2 rgb data sampling 8.3.3 clamp pulse generation 8.3.4 gain correction pulse generation 8.3.5 yuv data sampling 8.4 video mode and synchronization signal detection 8.5 memory interface and de-interlacer unit 8.5.1 memory interface limitations 8.5.2 initialization of external memory 8.5.3 frame and field memory 8.5.4 frame recovery 8.6 scaling 8.6.1 downscaling 8.6.2 upscaling 8.6.3 upscaler transition function 8.7 panning unit 8.8 overlay port 8.8.1 overlay insertion 8.8.2 sync generation 8.8.3 data sampling 8.8.4 ovclk gating 8.9 colour space matrix 8.10 colour correction 8.11 on screen display 8.11.1 osd generals 8.11.2 osd window 8.11.3 osd character matrix 8.12 temporal dithering (frame rate controller) 8.13 output interface 8.13.1 general 8.13.2 frame generation 8.13.3 timing reference signals 9 limiting values 10 characteristics 11 timing characteristics 12 application information 13 package outline 14 soldering 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 definitions 16 life support applications 17 purchase of philips i 2 c components
1999 may 11 3 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 1 features 1.1 rgb video input digital single (24-bit) or dual (48-bit) channel rgb input data input of sampled rgb data with a pixel frequency of maximum 150 mhz free definable data acquisition offsets and vertical window size in single pixel increments, horizontal window size in double pixel increments programmable pulses for adc clamping and adc gain correction detection of presence of sync signals, and of their polarities support for auto-adjustment functions for sample clock frequency, phase, vertical and horizontal sample offset, as well as colour adjustment maximum supported resolution of 1280 1024 dots super extended graphics adapter (sxga) support for detection of the applied graphics mode (multi-sync). 1.2 yuv video input pin sharing between yuv and rgb input port yuv 4 : 4 : 4, yuv 4 : 2 : 2, yuv 4 : 2 : 2 with ccir 656 codes, yuv 4:1:1 input of interlaced and non-interlaced digital video data maximum picture resolution of 1024 1024 pixels for interlaced or non-interlaced video input of video data at maximum 75 mhz free definable data acquisition offsets and window in double pixel or single line increments yuv to rgb colour space conversion. 1.3 video processing colour correction look-up table (lut) phase correct up and downscaling of the rgb data fully programmable scaling ratios independent horizontal and vertical scaling engine free definable position of the scaled input picture inside the output picture with programmable border colour de-interlacing unit for digital yuv video data zoom up to full-screen resolution of the de-interlaced yuv video stream via the main scaler. 1.4 on screen display character based internal on screen display (osd) programmable character matrix sizes of either 24 24 pixels (42 characters available) or 12 16 pixels (128 characters available) programmable width and height of the osd window, built from maximum 1152 characters 8 different colours for foreground and background inclusive transparent colours overlay port for external osd controller. 1.5 video output single pixel/clock (24-bit) or double pixel/clock (48-bit) digital rgb output generation of synchronization and validation signals for the thin film transistor (tft) display frame rate control (temporal dithering) for displaying true colour graphics on high colour displays free programmable timing for displays of several manufacturers. 1.6 memory interface support of both 1m 16 sdram, 256k 32 sgram or 128k 32 sgram devices maximum memory clock frequency of 125 mhz scalable memory size built of either 2, 3 or 4 sdram, or of 1 or 2 sgram devices special mode for operation without external memory. 1.7 miscellaneous internal phase-locked loop (pll) for memory and panel clock generation from the system clock i 2 c-bus interface with 2 selectable addresses boundary scan test circuit and joint test action group (jtag) test controller.
1999 may 11 4 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 2 general description the SAA6721e is a graphics engine, which converts digital rgb or yuv data into video signals suitable for tft displays. it supports sxga input resolution as well as true colour. independent horizontal and vertical up and downscaling can display the input data arbitrarily on the connected tft display. multi-sync capability allows the applied graphics mode to be detected. overlay signals can be generated either by an internal osd generator or supplied via the overlay port from an external osd controller. the SAA6721e must be embedded into a system containing a microcontroller with an i 2 c-bus serial interface. for multi-sync capabilities a frame buffer built from sgram or sdram is needed. the size of this frame buffer depends on the maximum resolution and bandwidth needed for the application. for converting the analog rgb stream into a digital data stream one or two adcs with 3 channels each for r, g and b are needed. if the yuv input is used, a video front-end chip such as the saa7113 must be used in front of the yuv port. 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 600 840 ma v i input voltages lvttl compatible v o output voltages memory port lvttl compatible output voltages tft port cmos compatible t amb ambient temperature 0 - 70 c type number package name description version SAA6721e bga292 plastic ball grid array package; 292 balls; body 27 27 1.75 mm sot489-1
1999 may 11 5 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 5 block diagram h andbook, full pagewidth mhb241 SAA6721e i 2 c-bus interface line memory rgb/yuv input interface temporal dithering jtag controller global control unit mode/sync detection auto adjustment controller frequency, phase and colour information input frame size and sync information osd overlay port memory interface de-interlacer colour correction on screen display up scaler down scaler scl sda sad int tdo tdi ba tms tclk ovvs ovhs ovclk ovact mclko v ssd v ddd v ss(pll) v dd(pll) panning unit ovb2 to ovb0 ova2 to ova0 a10 to a0 dq63 to dq0 vpa7 to vpa0 vpb7 to vpb0 vpc7 to vpc0 vpd7 to vpd0 vpe7 to vpe0 vpf7 to vpf0 par7 to par0 pag7 to pag0 pab7 to pab0 pbr7 to pbr0 pbg7 to pbg0 pbb7 to pbb0 pvs phs pde output interface pclk clamp vhs vvs vclk gainc rst ras cas we trst dqm 2 divider panel clock memory clock rgb raw data rgb/yuv data pll mclki clk yuv rgb fig.1 block diagram.
1999 may 11 6 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 6 pinning information table 1 symbol pin port i/o (1) description vclk n1 rgb/yuv input input rgb/yuv sample clock vvs m3 rgb/yuv input input rgb/yuv vertical sync vhs m2 rgb/yuv input input rgb/yuv horizontal sync vpa7 c7 rgb/yuv input input video input port a; rgb port 0 red channel or yuv port luminance vpa6 a6 rgb/yuv input input vpa5 b6 rgb/yuv input input vpa4 c6 rgb/yuv input input vpa3 a5 rgb/yuv input input vpa2 d5 rgb/yuv input input vpa1 b5 rgb/yuv input input vpa0 c5 rgb/yuv input input fig.2 pin configuration. handbook, halfpage mhb242 SAA6721e a b c d e f h k g j l m n p r t u v w y 2468101214161820 135791113151719
1999 may 11 7 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e vpb7 a4 rgb/yuv input input video input port b; rgb port 0 green channel or yuv port chrominance vpb6 b4 rgb/yuv input input vpb5 c4 rgb/yuv input input vpb4 a3 rgb/yuv input input vpb3 b3 rgb/yuv input input vpb2 c3 rgb/yuv input input vpb1 a2 rgb/yuv input input vpb0 b2 rgb/yuv input input vpc7 b1 rgb/yuv input input video input port c; rgb port 0 blue channel or yuv port chrominance vpc6 c2 rgb/yuv input input vpc5 c1 rgb/yuv input input vpc4 d3 rgb/yuv input input vpc3 d2 rgb/yuv input input vpc2 d1 rgb/yuv input input vpc1 e3 rgb/yuv input input vpc0 e2 rgb/yuv input input vpd7 e4 rgb/yuv input input video input port d; rgb port 1 red channel or yuv data quali?er port (vpd7 = cref clock gating signal; vpd6 = href active horizontal video) vpd6 e1 rgb/yuv input input vpd5 f3 rgb/yuv input input vpd4 f2 rgb/yuv input input vpd3 f1 rgb/yuv input input vpd2 g3 rgb/yuv input input vpd1 g2 rgb/yuv input input vpd0 g4 rgb/yuv input input vpe7 g1 rgb/yuv input input video input port e; rgb port 1 green channel vpe6 h3 rgb/yuv input input vpe5 h2 rgb/yuv input input vpe4 h1 rgb/yuv input input vpe3 j2 rgb/yuv input input vpe2 j4 rgb/yuv input input vpe1 j1 rgb/yuv input input vpe0 k3 rgb/yuv input input vpf7 k2 rgb/yuv input input video input port f; rgb port 1 blue channel vpf6 k1 rgb/yuv input input vpf5 l1 rgb/yuv input input vpf4 l4 rgb/yuv input input vpf3 l2 rgb/yuv input input vpf2 l3 rgb/yuv input input vpf1 m1 rgb/yuv input input vpf0 m4 rgb/yuv input input symbol pin port i/o (1) description
1999 may 11 8 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e clamp n2 rgb/yuv input output clamp pulse for analog-to-digital converter gainc n3 rgb/yuv input output gain correction pulse for analog-to-digital converter pclk y13 panel interface output panel clock pvs v12 panel interface output panel vertical sync phs w12 panel interface output panel horizontal sync pde u12 panel interface output panel data enable par7 p1 panel interface output panel port a red channel par6 p4 panel interface output par5 p2 panel interface output par4 p3 panel interface output par3 r1 panel interface output par2 r2 panel interface output par1 r3 panel interface output par0 t1 panel interface output pag7 t4 panel interface output panel port a green channel pag6 t2 panel interface output pag5 t3 panel interface output pag4 u1 panel interface output pag3 u2 panel interface output pag2 v1 panel interface output pag1 v2 panel interface output pag0 w1 panel interface output pab7 y1 panel interface output panel port a blue channel pab6 w2 panel interface output pab5 y2 panel interface output pab4 v3 panel interface output pab3 w3 panel interface output pab2 y3 panel interface output pab1 v4 panel interface output pab0 y4 panel interface output pbr7 v5 panel interface output panel port b red channel pbr6 w5 panel interface output pbr5 y5 panel interface output pbr4 v6 panel interface output pbr3 w6 panel interface output pbr2 y6 panel interface output pbr1 v7 panel interface output pbr0 w7 panel interface output symbol pin port i/o (1) description
1999 may 11 9 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e pbg7 y7 panel interface output panel port b green channel pbg6 v8 panel interface output pbg5 w8 panel interface output pbg4 y8 panel interface output pbg3 v9 panel interface output pbg2 w9 panel interface output pbg1 u9 panel interface output pbg0 y9 panel interface output pbb7 v10 panel interface output panel port b blue channel pbb6 w10 panel interface output pbb5 y10 panel interface output pbb4 y11 panel interface output pbb3 u11 panel interface output pbb2 w11 panel interface output pbb1 v11 panel interface output pbb0 y12 panel interface output scl v18 i 2 c-bus interface input i 2 c-bus interface clock line sda w18 input/output i 2 c-bus interface data line sad y17 input i 2 c-bus address select: 0 = 74h, 1 = 76h ovclk y16 overlay output overlay port clock ovvs w16 overlay output overlay port vertical sync ovhs v15 overlay output overlay port horizontal sync ovact v16 overlay input overlay port pixel active ova0 y14 overlay input overlay port input pixel a ova1 v13 overlay input ova2 w13 overlay input ovb0 y15 overlay input overlay port input pixel b ovb1 v14 overlay input ovb2 w14 overlay input mclko a17 memory interface output memory clock output ras a18 memory interface output memory row address strobe (ras) signal (active low) cas c17 memory interface output memory column address strobe (cas) signal (active low) we d16 memory interface output memory write enable (we) signal (active low) dqm t17 memory interface output memory data mask (active low) symbol pin port i/o (1) description
1999 may 11 10 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e a0 a20 memory interface output memory address bus a1 c20 memory interface output a2 d20 memory interface output a3 e19 memory interface output a4 f18 memory interface output a5 e17 memory interface output a6 e18 memory interface output a7 c19 memory interface output a8 c18 memory interface output a9 d18 memory interface output a10 b19 memory interface output ba a19 memory interface output memory bank select dq0 m20 memory interface input/output memory data bus dq1 m19 memory interface input/output dq2 n20 memory interface input/output dq3 n19 memory interface input/output dq4 p19 memory interface input/output dq5 r19 memory interface input/output dq6 t20 memory interface input/output dq7 t19 memory interface input/output dq8 t18 memory interface input/output dq9 r18 memory interface input/output dq10 p18 memory interface input/output dq11 p17 memory interface input/output dq12 n18 memory interface input/output dq13 m18 memory interface input/output dq14 m17 memory interface input/output dq15 l19 memory interface input/output dq16 e20 memory interface input/output dq17 f20 memory interface input/output dq18 g20 memory interface input/output dq19 h20 memory interface input/output dq20 j20 memory interface input/output dq21 k19 memory interface input/output dq22 k20 memory interface input/output dq23 l20 memory interface input/output dq24 k17 memory interface input/output dq25 k18 memory interface input/output dq26 j19 memory interface input/output dq27 j18 memory interface input/output dq28 h19 memory interface input/output symbol pin port i/o (1) description
1999 may 11 11 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e dq29 h18 memory interface input/output memory data bus dq30 g18 memory interface input/output dq31 f19 memory interface input/output dq32 a12 memory interface input/output dq33 b12 memory interface input/output dq34 a13 memory interface input/output dq35 b13 memory interface input/output dq36 a14 memory interface input/output dq37 b14 memory interface input/output dq38 a15 memory interface input/output dq39 b15 memory interface input/output dq40 a16 memory interface input/output dq41 c15 memory interface input/output dq42 c14 memory interface input/output dq43 d14 memory interface input/output dq44 c13 memory interface input/output dq45 c12 memory interface input/output dq46 d12 memory interface input/output dq47 c11 memory interface input/output dq48 b7 memory interface input/output dq49 a7 memory interface input/output dq50 b8 memory interface input/output dq51 a8 memory interface input/output dq52 b9 memory interface input/output dq53 a9 memory interface input/output dq54 b10 memory interface input/output dq55 a10 memory interface input/output dq56 b11 memory interface input/output dq57 a11 memory interface input/output dq58 d10 memory interface input/output dq59 c10 memory interface input/output dq60 d9 memory interface input/output dq61 c9 memory interface input/output dq62 c8 memory interface input/output dq63 d7 memory interface input/output tclk u19 jtag test controller input jtag test controller clock; note 2 trst w17 input jtag test controller reset (active low); note 2 tdi u18 input jtag test data input; note 2 tms v19 input jtag test mode select; note 2 tdo w19 output jtag test data output symbol pin port i/o (1) description
1999 may 11 12 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e clk y19 miscellaneous input system and panel clock rst y20 input system reset (active low) int y18 output mode detection interrupt (active low) mclki w20 input memory clock input v ssd a1 -- digital ground supply d4 d8 d13 d17 h4 h17 n4 n17 u4 u8 u13 u17 v ddd d6 -- digital supply voltage d11 d15 f4 f17 k4 l17 r4 r17 u6 u10 u15 v ss(pll) v17 -- ground supply for internal pll circuitry v dd(pll) u16 -- supply voltage for internal pll circuitry n.c. b16 -- not connected n.c. b17 -- not connected n.c. b18 -- not connected n.c. b20 -- not connected n.c. c16 -- not connected n.c. d19 -- not connected n.c. g17 -- not connected n.c. g19 -- not connected n.c. j3 -- not connected n.c. j17 -- not connected symbol pin port i/o (1) description
1999 may 11 13 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e notes 1. generally all inputs are 5 v tolerant ttl inputs. all outputs are cmos, except the memory interface ports, which are lvttl compatible. 2. connect to ground when not using the jtag controller. n.c. l18 -- not connected n.c. p20 -- not connected n.c. r20 -- not connected n.c. u3 -- not connected n.c. u5 -- not connected n.c. u7 -- not connected n.c. u14 -- not connected n.c. u20 -- not connected n.c. v20 -- not connected n.c. w4 -- not connected n.c. w15 -- not connected symbol pin port i/o (1) description 7 functional description 7.1 data path input video data is sampled either as rgb data in single pixels from only one adc or in double pixels in interleaved format from two adcs. alternatively the input interface can sample interlaced or non-interlaced yuv data. the clock for sampling the data will always be provided from external circuitry. the video stream will be adapted from the input frame rate to the output frame rate needed by the panel. therefore a frame buffer built of sdrams or sgrams is used. if the panel supports the incoming frame rate from the rgb port, the adaption can be done without external memory. if the video stream is in interlaced format the memory interface activates its de-interlacing unit. if zooming must be performed the upscaler behind the memory interface will be enabled. for downscaling the downscaler in front of the memory interface in the data path will be used. a colour correction can be done via a look-up table. the resulting video stream can now be positioned elsewhere in the output data stream by the panning unit. if an external osd controller is embedded into the system, its osd window will be put into the video stream by the osd overlay port. additionally the internal osd will be inserted in the next stage. the temporal dithering allows true colour pictures to be displayed on high colour panels. the output interface provides the timing and control signals necessary for the connected panel. 7.2 system clocks 7.2.1 i nput interface clock (vclk) this clock is used for sampling the incoming rgb or yuv data stream. in rgb mode this clock varies from 25 to 150 mhz in single adc mode. if two adcs are used the rgb input clock is between 12.5 and 75 mhz. in yuv mode the clock lies in the range of approximately 30 mhz. the clocks are generated from external devices. the rgb clock can be generated by the external adcs or an external video pll. the yuv clock must be generated by the video decoder which also provides the yuv video data. 7.2.2 m emory interface clock (mclki) the memory clock is the synchronous clock for the external frame buffer. depending on the bandwidth needed by the application, and the connected sdram or sgram devices, the clock varies from 83 to 125 mhz. it can be generated internally by the pll from the system clock (clk), or by an external quartz oscillator. if the internal pll is used, the memory clock frequency can be derived from the following formula: where n = pre-divider ratio and f_system = clock at pin clk. f_memory f_system n ----------------------- - 16 =
1999 may 11 14 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 7.2.3 i 2 c- bus interface clock (scl) this clock drives the interface to the external microcontroller. its frequency range is from 100 khz to 1 mhz. 7.2.4 s ystem clock (clk) this clock is used to drive the internal pll. the frequency range is from 24 to 50 mhz. 7.2.5 tft panel clock (pclk) this clock is the timing reference for the panel. the frequency is the same as the system clock, or it can be generated from the internal pll by using the following formula: where n = pre-divider ratio and m = post-divider ratio. 7.3 rgb input port the rgb input port can operate in two modes; single pixel mode (24 bits) and double pixel mode (48 bits). for single pixel mode only ports vpa7 to vpa0, vpb7 to vpb0, and vpc7 to vpc0 are internally sampled. for double pixel mode two pixels must be provided at the rgb input port. f_tft f_system n ----------------------- - 32 m ------ = therefore ports vpd7 to vpd0, vpe7 to vpe0, and vpf7 to vpf0 are also needed. the vpa/b/c ports are sampled on the rising edge of the rgb input clock (vclk), and the vpd/e/f ports on the falling edge (see fig.3). the synchronization pulses from the graphics card are used to identify the frame outline. the vertical synchronization pulse is connected to pin vvs, and the horizontal synchronization pulse is connected to pin vhs. for calibrating the connected analog-to-digital converter (adc) the SAA6721e delivers a clamp pulse at pin clamp, and a gain correction pulse at pin gainc (see fig.4). the sample window of the rgb input port is controlled by four counters; horizontal and vertical offset, and horizontal and vertical window size. the offset counters start at the inactive or second edge of their corresponding synchronization signal. fig.3 rgb input port timing. handbook, full pagewidth vclk vpa/b/c vpd/e/f mhb243
1999 may 11 15 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e fig.4 clamp and gain correction pulses. handbook, full pagewidth mhb244 vhs clamp rgb data gainc blanking 7.4 yuv input port the yuv input port supports interlaced video streams and provides an easy connection to most common decoder ics. it consists of the luminance port vpa7 to vpa0, the chrominance port vpb7 to vpb0, and eventually vpc7 to vpc0, which are ccir 601 level compatible (y: 16 to 235, and uv: 16 to 240). supported at this port are the formats yuv 4 : 1 : 1, yuv4:2:2 and yuv 4:2:2 with ccir 656 codes (see table 2). yuv 4:4:4 data can be applied at vpa7 to vpa0 (y), vpb7 to vpb0 (u), and vpc7 to vpc0 (v). input data is sampled with respect to the clock at pin vclk if pin vpd7 (cref) is asserted. the start of active video data in a line is marked by the rising edge at pin vpd6 (href) and the end of valid video data is marked by the falling edge at pin vpd6. figure 5 illustrates this at a yuv 4 :2:2 example. fig.5 cref and href timing. handbook, full pagewidth mhb245 vclk cref href y0 xx y719 y6 y5 ... y3 y2 y1 u0 xx v718 u718 v716 ... v2 u2 v0 xx xx y7 to y0 uv7 to uv0
1999 may 11 16 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e table 2 yuv input formats signal 4:1:1 format 4:2:2 format ccir 656 y7 y07 y17 y27 y37 y07 y17 u07 y07 v07 y17 y6 y06 y16 y26 y36 y06 y16 u06 y06 v06 y16 y5 y05 y15 y25 y35 y05 y15 u05 y05 v05 y15 y4 y04 y14 y24 y34 y04 y14 u04 y04 v04 y14 y3 y03 y13 y23 y33 y03 y13 u03 y03 v03 y13 y2 y02 y12 y22 y32 y02 y12 u02 y02 v02 y12 y1 y01 y11 y21 y31 y01 y11 u01 y01 v01 y11 y0 y00 y10 y20 y30 y00 y10 u00 y00 v00 y10 uv7 u07 u05 u03 u01 u07 v07 x x x x uv6 u06 u04 u02 u00 u06 v06 x x x x uv5 v07 v05 v03 v01 u05 v05 x x x x uv4 v06 v04 v02 v00 u04 v04 x x x x uv3 xxxxu03v03xxxx uv2 xxxxu02v02xxxx uv1 xxxxu01v01xxxx uv0 xxxxu00v00xxxx data frequency 1 2 vclk 1 2 vclk vclk for yuv 4 :4:4 the y, u, and v components are available in parallel. if non-interlaced video data is applied, it is treated as odd fields. interlaced video data is sampled odd field, even field, odd field, even field, etc. if there are equal subsequent frames, only the first of these frames will be sampled. the decoding of odd and even fields is done with href. in ccir 656 data streams the included codes are used for identifying even and odd frames, blanking and active video data. the codes start with the byte sequence ff 00 00, followed by the reference code byte; see figs 6 and 7. fig.6 ccir 656 sav code. handbook, full pagewidth mhb246 vclk ff ... y1 v0 y0 u0 sav 00 00 xx y7 to y0 fig.7 ccir 656 eav code. handbook, full pagewidth mhb247 vclk u718 xx eav 00 00 ff y719 v718 y718 ... y7 to y0
1999 may 11 17 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e the ccir 656 code byte contains vertical and horizontal blanking as well as odd and even field information, the protection bits p3 to p0 are ignored. table 3 ccir 656 code byte notes 1. f = 0: odd field (field 1); f = 1: even field (field 2). 2. v = 0: in active field lines; v = 1: in field blanking. 3. h = 0: sav (start of active video); h = 1: eav (end of active video). the sample window of the yuv input port is controlled by four counters; horizontal and vertical offset, and horizontal and vertical window size. the vertical offset counter starts counting from the inactive or second edge of its corresponding reference signal. the horizontal offset counter starts with the active edge of the href signal. 7.5 tft output port the tft output port consists of two pixel ports (a and b), each containing red, green and blue colour information with a resolution of 8 bits per colour. the first pixel port is mapped to par7 to par0, pag7 to pag0, and pab7 to pab0. the second port is mapped to pbr7 to pbr0, pbg7 to pbg0, and pbb7 to pbb0. the vertical and horizontal synchronization signals are mapped to pins pvs and phs. a data validation signal framing visible pixels is available at pin pde. all of the above mentioned signals are synchronized to the output clock at pin pclk. the active edge of this clock is programmable. 7.5.1 s ingle pixel mode the single pixel mode is designed to support tft panels with single pixel input, and for direct connection of panel link transmitters. only the first pixel port par7 to par0, pag7 to pag0, and pab7 to pab0 is used. the data is applied at double the frequency in comparison to the double pixel output mode. msb lsb 76543210 1f (1) v (2) h (3) p3 p2 p1 p0 7.5.2 d ouble pixel mode the double pixel mode is used for direct connection of tft panels with double pixel input. both output ports are used. the first pixel is applied at port a, and the second at port b. 7.6 memory port the memory port connects the SAA6721e to the external frame buffer. this frame memory can be built from either 1m 16 sdram or 256k 32 sgram devices. supported are ram devices with clock frequencies up to 125 mhz. this clock can be provided either by the internal pll, or externally be applied to pin mclki. the memory data bus is split into 4 ports: port 0 (dq0 to dq15), port 1 (dq16 to dq31), port 2 (dq32 to dq47) and port 3 (dq48 to dq63). to adapt the external memory to the needs of the application by means of memory size and bandwidth, it is possible to scale the external memory by using only the number of subsequent ports needed to build up the frame buffer and to achieve the memory bandwidth. as a second step for bandwidth optimization several speed grades of memory devices can be used. 7.6.1 sdram memory configuration sdrams are available in sizes from 16 mbits. for this application a wide data bus is required, so that at least 1m 16 devices must be used. to achieve the desired bandwidth, 2 to 4 devices must be used in parallel, which results in a frame buffer size of 4 to 8 mbytes. but only half of this memory will be used by the SAA6721e. the memory port of the SAA6721e can be divided into 4 sdram channels. each channel is 16 bits wide, and provides in high speed channel (hsc) mode with a 125 mhz memory clock and an effective bandwidth of 228 mbits/s. a medium speed channel (msc) with a 100 mhz memory clock gives an effective bandwidth of 182 mbits/s, 91% effective bandwidth assumed. table 4 gives the channel configuration for several input and panel resolutions.
1999 may 11 18 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e table 4 sdram channel con?gurations notes 1. 36 mhz clock frequency. 2. 50 mhz clock frequency. input resolution svga (800 600) xga (1024 768) sxga (1280 1024) 60 hz 75 hz 60 hz 75 hz 60 hz 75 hz panel 2 mbits frame buffer needed 3 mbits frame buffer needed 4 mbits frame buffer needed xga (1) 288 mbits/s bandwidth; 2 hsc or 2 msc 319 mbits/s bandwidth; 2 hsc or 2 msc 411 mbits/s bandwidth; 2 hsc or 3 msc 452 mbits/s bandwidth; 2 hsc or 3 msc 475 mbits/s bandwidth; 3 hsc or 3 msc 540 mbits/s bandwidth; 3 hsc or 3 msc sxga (2) 307 mbits/s bandwidth; 2 hsc or 2 msc 337 mbits/s bandwidth; 2 hsc or 2 msc 435 mbits/s bandwidth; 2 hsc or 3 msc 476 mbits/s bandwidth; 3 hsc or 3 msc 624 mbits/s bandwidth; 3 hsc or 4 msc 705 mbits/s bandwidth; 4 hsc or 4 msc 7.6.2 sgram memory configuration sgram devices organized to 256k 32 bits are available, and feature the wide data bus for high speed applications. with these devices a frame buffer can be built, without wasting memory because of bandwidth. in case of sgram usage, the memory data bus of the SAA6721e can be split into 2 channels of 32 bits each. each channel gives, in hsc mode with 125 mhz clock frequency, an effective bandwidth of 456 mbits/s; and in msc mode, with 100 mhz clock speed, an effective bandwidth of 364 mbits/s. table 5 gives the channel configuration for several input and panel resolutions. table 5 sgram channel con?gurations notes 1. 36 mhz clock frequency. 2. 50 mhz clock frequency. input resolution svga (800 600) xga (1024 768) sxga (1280 1024) 60 hz 75 hz 60 hz 75 hz 60 hz 75 hz panel 2 mbits frame buffer needed 3 mbits frame buffer needed 4 mbits frame buffer needed xga (1) 288 mbits/s bandwidth; 1 hsc or 1 msc 319 mbits/s bandwidth; 1 hsc or 1 msc 411 mbits/s bandwidth; 1 hsc or 2 msc 452 mbits/s bandwidth; 1 hsc or 2 msc 475 mbits/s bandwidth; 2 hsc or 2 msc 540 mbits/s bandwidth; 2 hsc or 2 msc sxga (2) 307 mbits/s bandwidth; 1 hsc or 1 msc 337 mbits/s bandwidth; 1 hsc or 1 msc 435 mbits/s bandwidth; 1 hsc or 2 msc 476 mbits/s bandwidth; 2 hsc or 2 msc 624 mbits/s bandwidth; 2 hsc or 2 msc 705 mbits/s bandwidth; 2 hsc or 2 msc
1999 may 11 19 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 7.7 i 2 c-bus interface this serial interface consists of only two signals, the serial clock line (scl) and the serial data line (sda). the maximum supported frequency on this bus is 1 mhz. spikes with a maximum pulse length of 50 ns are suppressed by the internal input filter. the SAA6721e operates as a slave and cannot initiate any data transfer, so the clock line is always input. via the data line, data is transmitted and received, so this pin must be input/output. the scl and sda lines are driven by open-drain stages and pull-up resistors. when a logic 0 is applied, the bus is set to ground level via the output buffers. when a logic 1 is applied, the output buffer switches to 3-state and the pull-up resistors pull the bus up to +5 v. data transfer changes on sda are allowed only when scl is low. data is sampled on the positive edge of scl. in idle state the output buffers are in 3-state, and the bus is high. a data transfer must be initiated by an i 2 c-bus master device. this is done by sending a start condition when sda changes from high to low when scl is high (see fig.8). the device address of the SAA6721e must then be sent with the desired i/o direction. if the SAA6721e reads its device address, it acknowledges this by sending a single bit ack to the master. if write mode was selected, the master sends the register address to be written and then the data bytes. if read mode was selected, the SAA6721e sends the data bytes starting from the last address accessed either by write command or the next address at a read command. all byte transfers are acknowledged from the receiving device. the data transfer is aborted by sending a stop condition, when sda changes from low to high when scl is high (see fig.9). if a new address has to be read or written, it is possible to send a new start condition without a preceding stop condition. in this case the bus is still occupied by the master, and it can initiate a new data transfer. this is useful for read activities, where at first the register address must be sent in write mode and after that a read command will be sent to read data from this and following addresses. fig.8 start of a data transfer. handbook, full pagewidth mhb248 scl sda a4 a1 a2 a3 a6 a5 ack r/w a0 r5 r7 r6 start condition acknowledge fig.9 end of a data transfer. handbook, full pagewidth mhb249 scl sda d7 d4 d5 d6 d1 d0 ack d2 d3 a/a d1 d0 stop condition acknowledge/ not acknowledge
1999 may 11 20 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e if the data transfer was a read transfer and the master was receiver, the master must not generate an acknowledge before the stop condition. 7.8 de-interlacing algorithms the SAA6721e features several de-interlacing algorithms for processing interlaced video data. depending on the algorithm different memory bandwidths and field memories are needed. 7.8.1 s tatic mesh mode this mode allows de-interlacing without any image processing and filtering. a field store for 2 fields is necessary. de-interlacing is achieved by simply putting lines together in the right order from the odd and even fields in the field store and generating the output frame. 7.8.2 s patial filtering the spatial filtering mode requires 2 field memories, but only one memory is used at a time. for the calculation of the whole frame from an odd field, the missing even lines are interpolated from the odd lines before and after. processing of the even field is done in the same way. 7.8.3 t emporal filtering the filtering algorithm needs 4 field memories and will be applied temporally to subsequent fields. the missing even line in an odd frame will be calculated by interpolation from the corresponding even lines in the even fields before and after. the odd line handling is done in the same way. 7.9 scaling algorithm the SAA6721e features different scaling engines for up and downscaling, for both horizontal and vertical processing. the horizontal scaling engines are independent from each other. the vertical scaling engines share the line buffer, so they cannot operate in parallel. 7.9.1 u pscaling the upscaling engine is used for enlarging the incoming video frames. it can be used for zooming both rgb and yuv video data. the magnification can be programmed individually for horizontal and vertical scaling. the maximum scaling factor for both directions is 64. the implemented filter algorithm (see fig.10) uses interpolation with pixel enhancement, based on a free programmable transition function. it is therefore possible to define the transition between two calculated pixels to obtain different sharpness characteristics. this transition function must be defined in the 7 bits 64 look-up table, with a number ranging from 0 to 64. different functions can be programmed for horizontal and vertical scaling. fig.10 interpolation function definition. (1) the linear interpolation results in smoothing the sharp edges of the original picture if a pixel must be calculated. (2) some kind of 1 x function results in sharper edges, because of the smaller transition interval. (3) phase correct pixel repetition can be done with this function. handbook, full pagewidth mhb250 ratio between input pixels a, b intensity of output pixel o ab o 0% a, 100% b 0% a, 100% b 100% a, 0% b 100% a, 0% b (1) (3) (2)
1999 may 11 21 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 7.9.2 d ownscaling the downscaling engine is used for reducing the incoming rgb data stream, i.e. for displaying high resolution input frames on panels with a smaller resolution. the scaling ratio can be programmed independently for both horizontal and vertical downscaling units. the algorithm uses pixel accumulation, achieving a minimum scaling factor of 1 64 . 8 system description 8.1 programming registers the SAA6721e is a highly integrated device with many features. to get the desired functionality and performance it must be programmed correctly. in general, before programming, the device must be switched to the internal reset state to prevent unwanted functions while changing the registers. after writing to all registers the internal reset can be released. there are some registers (mainly offset counters) that can be changed during data processing without an internal reset. all accesses to the on screen display can be done during data processing. table 6 i 2 c-bus device address bit sad = 0 the address is 74h, while bit sad = 1 the address is 76h. table 7 shows the programming model. msb lsb 011101sadr/ w table 7 programming register overview address r/w d7 d6 d5 d4 d3 d2 d1 d0 state 0 r reserved 1 r reserved 2 r/w iic_test_register[7 to 0] 3r intr rgb mode detection 4 r pos_ vsync pos_ hsync no_ vsync no_ hsync 5 r v_lines[7 to 0] 6 r v_lines[10 to 8] 7 r h_clocks[7 to 0] 8 r h_clocks[11 to 8] rgb auto-adjustment 9 w ref_line[7 to 0] 10 w ref_line[10 to 8] 11 w ref_pixel[7 to 0] 12 w ref_pixel[11 to 8] 13 w ref_colour[7 to 0] 14 r ref_pixel_red[7 to 0] 15 r ref_pixel_green[7 to 0] 16 r ref_pixel_blue[7 to 0] 17 r black_lines[7 to 0] 18 r black_pixels[7 to 0]
1999 may 11 22 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 19 r black_ pixels[8] 20 r non_black_lines[7 to 0] 21 r non_black_lines[10 to 8] 22 r non_black_pixels[7 to 0] 23 r non_black_pixels[11 to 8] general con?guration 24 w intr_clear single_ adc_mode no_ memory_ mode memory_ init reset_ input_path reset_ memory_ path reset_ proc_path 25 w yuv_clk_ mux csm_ bypass frc_on blank_ screen power_ down clock distribution 26 w por_mclk pre_div_ enable post_div_ enable pre_div_ half_clock post_div_ half_clock pll_enable pll_pclk pll_mclk 27 w pre_div_clock_p_high[3 to 0] pre_div_clock_p_low[3 to 0] 28 w pre_div_clock_n_high[3 to 0] pre_div_clock_n_low[3 to 0] 29 w pre_div_clock_n_offs[3 to 0] 30 w post_div_clock_p_high[3 to 0] post_div_clock_p_low[3 to 0] 31 w post_div_clock_n_high[3 to 0] post_div_clock_n_low[3 to 0] 32 w post_div_clock_n_offs[3 to 0] input interface 33 w rgb_interl_ on in_form_ on rgb_proc_ on adc_ sample_ seq gainc_pol clamp_pol vs_pol hs_pol 34 w ?eld_ reverse yuv_?eld_mode [1 and 0] yuv_input_mode [1 and 0] yuv_href_ pol yuv_cref_ pol 35 w v_offset[7 to 0] 36 w v_offset[10 to 8] 37 w h_offset[7 to 0] 38 w h_offset[11 to 8] 39 w v_length[7 to 0] 40 w v_length[10 to 8] 41 w h_length[7 to 0] 42 w h_length[11 to 8] 43 w clamp_on[7 to 0] 44 w clamp_off[7 to 0] 45 w gainc_on_delay[7 to 0] 46 w gainc_off_delay[7 to 0] address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 23 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e colour correction 47 w red_prog green_ prog blue_prog colour_ correction _on 48 w colour_index[7 to 0] 49 w (1) colour_value[7 to 0] memory interface/de-interlacing unit 50 w yuv422_ mode data_width[1 and 0] deint_mode[1 and 0] 51 w burst_seq_length[3 to 0] 52 w sdram_burst_length_code[2 to 0] sdram_burst_length[3 to 0] 53 w cas_latency[2 to 0] t_rcd[3 to 0] 54 w t_rrd[3 to 0] t_rp[3 to 0] 55 w t_wr[3 to 0] t_rc[3 to 0] 56 w ?eld1_row[7 to 0] 57 w ?eld1_row[10 to 8] 58 w ?eld1_column[7 to 0] 59 w ?eld2_row[7 to 0] 60 w ?eld2_row[10 to 8] 61 w ?eld2_column[7 to 0] 62 w ?eld3_row[7 to 0] 63 w ?eld3_row[10 to 8] 64 w ?eld3_column[7 to 0] 65 w ?eld4_row[7 to 0] 66 w ?eld4_row[10 to 8] 67 w ?eld4_column[7 to 0] 68 w frame_length[7 to 0] 69 w frame_length[10 to 8] 70 w line_length[7 to 0] 71 w line_length[11 to 8] 72 w blank_colour_red[7 to 0] 73 w blank_colour_green[7 to 0] 74 w blank_colour_blue[7 to 0] scaler 75 w down_v_ scaler_ mem up_v_ coeff_prog up_h_ coeff_prog up_v_ scaler_on up_h_ scaler_on down_v_ scaler_on down_h_ scaler_on 76 w up_v_incr[7 to 0] 77 w up_v_incr[11 to 8] 78 w up_v_corr[6 to 0] 79 w up_h_incr[7 to 0] address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 24 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 80 w up_h_incr[11 to 8] 81 w up_h_corr[6 to 0] 82 w down_v_incr[5 to 0] 83 w down_v_corr[6 to 0] 84 w down_h_incr[5 to 0] 85 w down_h_corr[6 to 0] 86 w coeff_index[5 to 0] 87 w (1) coeff_value[6 to 0] panning unit 88 w pic_v_offset[7 to 0] 89 w pic_v_offset[10 to 8] 90 w pic_h_offset[7 to 0] 91 w pic_h_offset[11 to 8] 92 w out_v_size[7 to 0] 93 w out_v_size[10 to 8] 94 w out_h_size[7 to 1] 0 95 w out_h_size[11 to 8] 96 w border_colour_red[7 to 0] 97 w border_colour_green[7 to 0] 98 w border_colour_blue[7 to 0] osd overlay port 99 w ovl_clk_ pol ovl_act_ pol ovl_vs_ pol ovl_hs_ pol clk_ gating_on sample_ edge ovl_ syncs_ active ovl_ insert_ active 100 w ovl_hs_start[7 to 0] 101 w ovl_hs_start[10 to 8] 102 w ovl_hs_length[7 to 0] 103 w ovl_hs_length[10 to 8] 104 w ovl_hs_latency[7 to 0] 105 w ovl_h_length[7 to 0] 106 w ovl_h_length[10 to 8] 107 w ovl_v_offset[7 to 0] 108 w ovl_v_offset[10 to 8] 109 w ovl_v_length[7 to 0] 110 w ovl_v_length[10 to 8] 111 w ovl_vs_start[7 to 0] 112 w ovl_vs_start[10 to 8] 113 w ovl_colour0_red[7 to 0] 114 w ovl_colour0_green[7 to 0] 115 w ovl_colour0_blue[7 to 0] address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 25 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 116 w ovl_colour1_red[7 to 0] 117 w ovl_colour1_green[7 to 0] 118 w ovl_colour1_blue[7 to 0] 119 w ovl_colour2_red[7 to 0] 120 w ovl_colour2_green[7 to 0] 121 w ovl_colour2_blue[7 to 0] 122 w ovl_colour3_red[7 to 0] 123 w ovl_colour3_green[7 to 0] 124 w ovl_colour3_blue[7 to 0] 125 w ovl_colour4_red[7 to 0] 126 w ovl_colour4_green[7 to 0] 127 w ovl_colour4_blue[7 to 0] 128 w ovl_colour5_red[7 to 0] 129 w ovl_colour5_green[7 to 0] 130 w ovl_colour5_blue[7 to 0] 131 w ovl_colour6_red[7 to 0] 132 w ovl_colour6_green[7 to 0] 133 w ovl_colour6_blue[7 to 0] 134 w ovl_colour7_red[7 to 0] 135 w ovl_colour7_green[7 to 0] 136 w ovl_colour7_blue[7 to 0] on screen display 137 w zoom2 char_size osd_ active 138 w osd_v_offset[7 to 0] 139 w osd_v_offset[10 to 8] 140 w osd_h_offset[7 to 0] 141 w osd_h_offset[11 to 8] 142 w osd_v_size[5 to 0] 143 w osd_h_size[5 to 0] 144 w osd_fg_colour0_red[7 to 0] 145 w osd_fg_colour0_green[7 to 0] 146 w osd_fg_colour0_blue[7 to 0] 147 w osd_fg_colour1_red[7 to 0] 148 w osd_fg_colour1_green[7 to 0] 149 w osd_fg_colour1_blue[7 to 0] 150 w osd_fg_colour2_red[7 to 0] 151 w osd_fg_colour2_green[7 to 0] 152 w osd_fg_colour2_blue[7 to 0] 153 w osd_fg_colour3_red[7 to 0] address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 26 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 154 w osd_fg_colour3_green[7 to 0] 155 w osd_fg_colour3_blue[7 to 0] 156 w osd_fg_colour4_red[7 to 0] 157 w osd_fg_colour4_green[7 to 0] 158 w osd_fg_colour4_blue[7 to 0] 159 w osd_fg_colour5_red[7 to 0] 160 w osd_fg_colour5_green[7 to 0] 161 w osd_fg_colour5_blue[7 to 0] 162 w osd_fg_colour6_red[7 to 0] 163 w osd_fg_colour6_green[7 to 0] 164 w osd_fg_colour6_blue[7 to 0] 165 w osd_fg_colour7_red[7 to 0] 166 w osd_fg_colour7_green[7 to 0] 167 w osd_fg_colour7_blue[7 to 0] 168 w osd_bg_colour0_red[7 to 0] 169 w osd_bg_colour0_green[7 to 0] 170 w osd_bg_colour0_blue[7 to 0] 171 w osd_bg_colour1_red[7 to 0] 172 w osd_bg_colour1_green[7 to 0] 173 w osd_bg_colour1_blue[7 to 0] 174 w osd_bg_colour2_red[7 to 0] 175 w osd_bg_colour2_green[7 to 0] 176 w osd_bg_colour2_blue[7 to 0] 177 w osd_bg_colour3_red[7 to 0] 178 w osd_bg_colour3_green[7 to 0] 179 w osd_bg_colour3_blue[7 to 0] 180 w osd_bg_colour4_red[7 to 0] 181 w osd_bg_colour4_green[7 to 0] 182 w osd_bg_colour4_blue[7 to 0] 183 w osd_bg_colour5_red[7 to 0] 184 w osd_bg_colour5_green[7 to 0] 185 w osd_bg_colour5_blue[7 to 0] 186 w osd_bg_colour6_red[7 to 0] 187 w osd_bg_colour6_green[7 to 0] 188 w osd_bg_colour6_blue[7 to 0] 189 w osd_bg_colour7_red[7 to 0] 190 w osd_bg_colour7_green[7 to 0] 191 w osd_bg_colour7_blue[7 to 0] 192 w osd_fg_ colour7_ transp osd_fg_ colour6_ transp osd_fg_ colour5_ transp osd_fg_ colour4_ transp osd_fg_ colour3_ transp osd_fg_ colour2_ transp osd_fg_ colour1_ transp osd_fg_ colour0_ transp address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 27 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 193 w osd_fg_ colour7_ alpha osd_fg_ colour6_ alpha osd_fg_ colour5_ alpha osd_fg_ colour4_ alpha osd_fg_ colour3_ alpha osd_fg_ colour2_ alpha osd_fg_ colour1_ alpha osd_fg_ colour0_ alpha 194 w osd_bg_ colour7_ transp osd_bg_ colour6_ transp osd_bg_ colour5_ transp osd_bg_ colour4_ transp osd_bg_ colour3_ transp osd_bg_ colour2_ transp osd_bg_ colour1_ transp osd_bg_ colour0_ transp 195 w osd_bg_ colour7_ alpha osd_bg_ colour6_ alpha osd_bg_ colour5_ alpha osd_bg_ colour4_ alpha osd_bg_ colour3_ alpha osd_bg_ colour2_ alpha osd_bg_ colour1_ alpha osd_bg_ colour0_ alpha on screen display window 196 w cursor_row[5 to 0] 197 w cursor_column[5 to 0] 198 w char_appearance [1 and 0] char_bg_colour[2 to 0] char_fg_colour[2 to 0] 199 w (1) char_code[6 to 0] on screen display character matrix 200 w char_code[6 to 0] 201 w (1) char_def[7 to 0] tft display interface 202 w vsync_pol hsync_pol de_pol clk_pol single_ pixel_ output 203 w line_sync sync_de_ act out_if_ enable blank_tft sync_ mode blank_ctrl border_ ctrl active_ctrl 204 w h_len_blank[7 to 0] 205 w h_len_blank[10 to 8] 206 w h_len_border[7 to 0] 207 w h_len_border[10 to 8] 208 w h_len_active[7 to 0] 209 w h_len_active[10 to 8] 210 w v_end[7 to 0] 211 w v_end[10 to 8] 212 w v_start[7 to 0] 213 w v_start[10 to 8] 214 w v_active[7 to 0] 215 w v_active[10 to 8] 216 w h_vs_start[7 to 0] 217 w h_vs_start[10 to 8] 218 w h_vs_end[7 to 0] 219 w h_vs_end[10 to 8] 220 w h_hs_start[7 to 0] 221 w h_hs_start[10 to 8] address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 28 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e note 1. register does not work with register address auto-increment, but with incrementing the address on which the operation is performed. table 8 detailed description of programming registers 222 w h_hs_end[7 to 0] 223 w h_hs_end[10 to 8] 224 w h_de_start[7 to 0] 225 w h_de_start[10 to 8] 226 w h_de_end[7 to 0] 227 w h_de_end[10 to 8] 228 w h_active_start[7 to 0] 229 w h_active_start[10 to 8] 230 w v_vs_end[7 to 0] 231 w v_vs_end[10 to 8] 232 w h_max_len[7 to 0] 233 w h_max_len[10 to 8] name subaddress r/w data state iic test register iic test register 2 r/w d7 to d0 s tate register interrupt state 3 r d0 interrupt active logic 0 interrupt not active logic 1 rgb mode detection s ync detect register hsync presence 4 r d0 hsync present logic 0 hsync not present logic 1 vsync presence d1 vsync present logic 0 vsync not present logic 1 hsync polarity d2 negative hsync logic 0 positive hsync logic 1 vsync polarity d3 negative vsync logic 0 positive vsync logic 1 address r/w d7 d6 d5 d4 d3 d2 d1 d0
1999 may 11 29 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e v ertical frame resolution number of lines between two vsyncs 5 and 6 r d10 to d0 h orizontal frame resolution number of clocks between two hsyncs 7 and 8 r d11 to d0 rgb auto adjustment r eference line position reference line for auto adjustment measurements 9 and 10 w d10 to d0 r eference pixel position reference pixel for auto adjustment measurements 11 and 12 w d11 to d0 r eference colour colour for selecting black or non-black pixels 13 w d7 to d0 r eference pixel colour red component red colour component of reference pixel 14 r d7 to d0 r eference pixel colour green component green colour component of reference pixel 15 r d7 to d0 r eference pixel colour blue component blue colour component of reference pixel 16 r d7 to d0 b lack lines counter number of black lines after vsync 17 r d7 to d0 b lack pixels counter number of black pixels after hsync 18 and 19 r d8 to d0 n on - black lines counter number of non-black lines after vsync 20 and 21 r d10 to d0 n on - black pixels counter number of non-black pixels after hsync 22 and 23 r d11 to d0 name subaddress r/w data
1999 may 11 30 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e general con?guration c onfiguration register 1 processing reset state 24 w d0 processing path not in reset state logic 0 processing path in reset state logic 1 memory reset state d1 memory path not in reset state logic 0 memory path in reset state logic 1 input reset state d2 input path not in reset state logic 0 input path in reset state logic 1 external memory initialization d3 no external memory initialization logic 0 start external memory initialization logic 1 external memory con?guration d4 external memory present logic 0 no external memory present logic 1 external adc con?guration d5 2 adcs connected logic 0 1 adc connected logic 1 interrupt acknowledge d6 no acknowledge logic 0 reset interrupt output to logic 1 logic 1 c onfiguration register 2 output interface power-down mode 25 w d0 normal processing logic 0 all outputs of output interface at low level logic 1 blank screen d1 normal data processing logic 0 blank screen generation after memory interface logic 1 output temporal dithering d2 no temporal dithering of output data stream logic 0 temporal dithering of output data logic 1 colour space conversion matrix d3 conversion yuv to rgb enabled logic 0 straight rgb processing enabled logic 1 yuv processing clock multiplexer d4 clock will be applied at pin vclk logic 0 clock will be applied at pin mclki logic 1 name subaddress r/w data
1999 may 11 31 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e clock distribution c lock multiplexing memory clock generation 26 w d0 memory clock is taken from pin mclki logic 0 memory clock is 1 2 pll clock logic 1 panel clock generation d1 panel clock is equal system clock logic 0 panel clock is generated by pll clock and post-divider logic 1 pll activation d2 pll disabled logic 0 pll enabled logic 1 pll post-divider precision d3 1 2 clock precision disabled logic 0 1 2 clock precision enabled logic 1 pll pre-divider precision d4 1 2 clock precision disabled logic 0 1 2 clock precision enabled logic 1 pll post-divider activation d5 pll post-divider disabled logic 0 pll post-divider enabled logic 1 pll pre-divider activation d6 pll pre-divider disabled logic 0 pll pre-divider enabled logic 1 external memory clock multiplexer d7 enable memory clock logic 0 use system clock as external memory clock logic 1 p re - divider p - counter pre-divider p-counter programming 27 w d7 to d0 p re - divider n - counter pre-divider n-counter programming 28 w d7 to d0 p re - divider n - offset pre-divider n-counter offset programming 29 w d3 to d0 p ost - divider p - counter post-divider p-counter programming 30 w d7 to d0 p ost - divider n - counter post-divider n-counter programming 31 w d7 to d0 p ost - divider n - offset post-divider n-counter offset programming 32 w d3 to d0 name subaddress r/w data
1999 may 11 32 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e input interface g eneral programming hsync polarity 33 w d0 hsync is active low, line starts at rising edge of pin vhs logic 0 hsync is active high, line starts at falling edge of pin vhs logic 1 vsync polarity d1 vsync is active low, line starts at rising edge of pin vvs logic 0 vsync is active high, line starts at falling edge of pin vvs logic 1 clamp pulse polarity d2 pulse is active low logic 0 pulse is active high logic 1 gain correction pulse polarity d3 pulse is active low logic 0 pulse is active high logic 1 adc sample sequence d4 adc 0 is sampled first after hsync (video input port a, b, c) logic 0 adc 1 is sampled first after hsync (video input port d, e, f) logic 1 rgb/yuv processing mode d5 yuv processing enabled logic 0 rgb processing enabled logic 1 input interface activation d6 no data sampling logic 0 data sampling enabled logic 1 interlaced rgb mode d7 non-interlaced rgb processing logic 0 interlaced rgb processing logic 1 name subaddress r/w data
1999 may 11 33 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e i nterlaced mode programming yuv cref polarity 34 w d0 yuv clock qualifier is active low logic 0 yuv clock qualifier is active high logic 1 yuv href polarity d1 active data qualifier is active low logic 0 active data qualifier is active high logic 1 yuv format d3 and d2 ccir 656 d3 = 0 and d2 = 0 4:1:1 format d3 = 0 and d2 = 1 4:2:2 format d3 = 1 and d2 = 0 4:4:4 format d3 = 1 and d2 = 1 yuv ?eld sampling mode d5 and d4 all incoming frames are captured d5 = 0 and d4 = 0 capture alternating fields only d5 = 0 and d4 = 1 capture odd fields only d5 = 1 and d4 = 0 capture even fields only d5 = 1 and d4 = 1 field reverse ?ag d6 keep original odd field identification logic 0 change field identification logic 1 v ertical sample offset vertical sample offset from vsync 35 and 36 w d10 to d0 h orizontal sample offset horizontal sample offset from hsync 37 and 38 w d11 to d0 v ertical sample length vertical sample window length 39 and 40 w d10 to d0 h orizontal sample length horizontal sample window length 41 and 42 w d11 to d0 c lamp pulse start start of clamp pulse after active edge of hsync 43 w d7 to d0 c lamp pulse end end of clamp pulse after active edge of hsync 44 w d7 to d0 g ain correction pulse start delay delay of start of gainc pulse from ?rst edge of hsync 45 w d7 to d0 g ain correction pulse end delay delay of end of pulse gainc from second edge of hsync 46 w d7 to d0 name subaddress r/w data
1999 may 11 34 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e colour correction p rogramming selector , activation colour correction activation 47 w d0 straight colour processing logic 0 colour substitution enabled logic 1 blue component programming d1 red component correction colour writing disabled logic 0 red component correction colour writing enabled logic 1 green component programming d2 red component correction colour writing disabled logic 0 red component correction colour writing enabled logic 1 red component programming d3 red component correction colour writing disabled logic 0 red component correction colour writing enabled logic 1 c olour index for look - up table writing colour component look-up table index 48 w d7 to d0 c olour value for look - up table writing colour component substitution value 49 w d7 to d0 memory interface/de-interlacing unit g eneral configuration de-interlacing mode 50 w d1 and d0 no de-interlacing d1 = 0 and d0 = 0 de-interlacing without filtering d1 = 0 and d0 = 1 de-interlacing with spatial filtering d1 = 1 and d0 = 0 de-interlacing with temporal filtering d1 = 1 and d0 = 1 external memory data bus width d3 and d2 32 bits (two 16-bit channels) d3 = 0 and d2 = 0 48 bits (three 16-bit channels) d3 = 0 and d2 = 1 64 bits (four 16-bit channels) d3 = 1 and d2 = 0 do not use d3 = 1 and d2 = 1 internal data path width d4 rgb and yuv 4:4:4 processing logic 0 yuv 4:2:2, yuv 4:1:1 and ccir 656 processing logic 1 a ccess burst length number of bursts per read/write access to sdram 51 w d3 to d0 sdram burst length sdram burst length 52 w d3 to d0 sdram initialization code for burst length d6 to d4 name subaddress r/w data
1999 may 11 35 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e sdram timing parameter 1; see t able 14 active to read or write delay (t rcd ) in clocks 53 w d3 to d0 cas latency (cl) in clocks d6 to d4 sdram timing parameter 2; see t able 14 precharge command period (t rp ) in clocks 54 w d3 to d0 active bank a to active band b command (t rrd ) in clocks d7 to d4 sdram timing parameter 3; see t able 14 auto refresh, active command period (t rc ) in clocks 55 w d3 to d0 write recovery time (t wr ) in clocks d7 to d4 f ield 1 start address ( row ) start address of ?eld 1 in external sdram memory (row) 56 and 57 w d10 to d0 f ield 1 start address ( column ) start address of ?eld 1 in external sdram memory (column) 58 w d7 to d0 f ield 2 start address ( row ) start address of ?eld 2 in external sdram memory (row) 59 and 60 w d10 to d0 f ield 2 start address ( column ) start address of ?eld 2 in external sdram memory (column) 61 w d7 to d0 f ield 3 start address ( row ) start address of ?eld 3 in external sdram memory (row) 62 and 63 w d10 to d0 f ield 3 start address ( column ) start address of ?eld 3 in external sdram memory (column) 64 w d7 to d0 f ield 4 start address ( row ) start address of ?eld 4 in external sdram memory (row) 65 and 66 w d10 to d0 f ield 4 start address ( column ) start address of ?eld 4 in external sdram memory (column) 67 w d7 to d0 o utput frame length vertical length of output frame after de-interlacing unit 68 and 69 w d10 to d0 o utput line length horizontal length of output frame after de-interlacing unit 70 and 71 w d11 to d0 b lank colour red component definition red colour component for blank screen generation 72 w d7 to d0 b lank colour green component definition green colour component for blank screen generation 73 w d7 to d0 b lank colour blue component definition blue colour component for blank screen generation 74 w d7 to d0 name subaddress r/w data
1999 may 11 36 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e scaler s caler configuration horizontal downscaler activation 75 w d0 horizontal downscaler disabled logic 0 horizontal downscaler enabled logic 1 vertical downscaler activation d1 vertical downscaler disabled logic 0 vertical downscaler enabled logic 1 horizontal upscaler activation d2 horizontal upscaler disabled logic 0 horizontal upscaler enabled logic 1 vertical upscaler activation d3 vertical upscaler disabled logic 0 vertical upscaler enabled logic 1 horizontal upscaling transition function programming d4 horizontal upscaling transition function writing disabled logic 0 horizontal upscaling transition function writing enabled logic 1 vertical upscaling transition function programming d5 vertical upscaling transition function writing disabled logic 0 vertical upscaling transition function writing enabled logic 1 line memory usage d6 line memory used by upscaling unit logic 0 line memory used by downscaling unit logic 1 v ertical upscale increment increment for vertical upscaling 76 and 77 w d11 to d0 v ertical upscale correction fraction of vertical upscaling increment ( 1 100 ) 78 w d6 to d0 h orizontal upscale increment increment for horizontal upscaling 79 and 80 w d11 to d0 h orizontal upscale correction fraction of horizontal upscaling increment ( 1 100 ) 81 w d6 to d0 v ertical downscale increment increment for vertical downscaling 82 w d5 to d0 v ertical downscale correction fraction of vertical downscaling increment ( 1 100 ) 83 w d6 to d0 h orizontal downscale increment increment for horizontal downscaling 84 w d5 to d0 name subaddress r/w data
1999 may 11 37 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e h orizontal downscale correction fraction of horizontal downscaling increment ( 1 100 ) 85 w d6 to d0 i ndex for coefficient table writing transition function look-up table index 86 w d5 to d0 c oefficient value for look - up table writing values of transition function 87 w d6 to d0 panning unit v ertical picture offset vertical input picture offset inside the output frame 88 and 89 w d10 to d0 h orizontal picture offset horizontal input picture offset inside the output frame 90 and 91 w d11 to d0 v ertical output frame length vertical output frame length 92 and 93 w d10 to d0 h orizontal output frame length horizontal output frame length 94 and 95 w d11 to d0 b order colour red component definition red colour component for border generation 96 w d7 to d0 b order colour green component definition green colour component for border generation 97 w d7 to d0 b order colour blue component definition blue colour component for border generation 98 w d7 to d0 name subaddress r/w data
1999 may 11 38 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e osd overlay port g eneral configuration osd overlay port activation 99 w d0 overlay information will not be inserted into data stream logic 0 overlay information will be inserted into data stream logic 1 sync pulse generation d1 no sync pulses will be generated logic 0 sync pulses will be generated logic 1 clock edge for sampling d2 data sampling at falling edge of clock at pin ovclk logic 0 data sampling at rising edge of clock at pin ovclk logic 1 clock gating d3 ovclk always enabled logic 0 ovclk enabled only during internal active video processing logic 1 horizontal sync polarity d4 active low horizontal sync pulse at pin ovhs logic 0 active high horizontal sync pulse at pin ovhs logic 1 vertical sync polarity d5 active low vertical sync pulse at pin ovvs logic 0 active high vertical sync pulse at pin ovvs logic 1 overlay port active pixel quali?er polarity d6 active low qualifier signal at pin ovact logic 0 active high qualifier signal at pin ovact logic 1 overlay port clock polarity d7 sync pulse change with respect to falling edge at pin ovclk logic 0 sync pulse change with respect to rising edge at pin ovclk logic 1 o verlay horizontal sync start start of horizontal sync pulse with respect to left frame border 100 and 101 w d10 to d0 o verlay horizontal sync length length of horizontal sync pulse 102 and 103 w d10 to d0 o verlay horizontal sync latency delay between start of horizontal sync and valid overlay data 104 w d7 to d0 o verlay window horizontal length horizontal length of overlay region 105 and 106 w d10 to d0 o verlay window vertical offset vertical offset of overlay region 107 and 108 w d10 to d0 o verlay window vertical length vertical length of overlay region 109 and 110 w d10 to d0 name subaddress r/w data
1999 may 11 39 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e o verlay vertical sync start start of vertical sync pulse with respect to top frame border 111 and 112 w d10 to d0 c olour 0 to 7 red component definition red colour component for overlay colour 0 to 7 113, 116, 119, 122, 125, 128, 131 and 134 wd7tod0 c olour 0 to 7 green component definition green colour component for overlay colour 0 to 7 114, 117, 120, 123, 126, 129, 132 and 135 wd7tod0 c olour 0 to 7 blue component definition blue colour component for overlay colour 0 to 7 115, 118, 121, 124, 127, 130, 133 and 136 wd7tod0 on screen display g eneral configuration osd activation 137 w d0 osd is not visible logic 0 osd is visible logic 1 osd character size d1 12 16 character matrix logic 0 24 24 character matrix logic 1 osd zoom d2 no zooming of osd window logic 0 zoom by 2 of osd window logic 1 osd window vertical offset vertical offset of osd window from left frame border in pixel 138 and 139 w d10 to d0 osd window horizontal offset horizontal offset of osd window from top frame border in pixel 140 and 141 w d11 to d0 osd window vertical size vertical size of osd window in characters 142 w d5 to d0 osd window horizontal size horizontal size of osd window in characters 143 w d5 to d0 f oreground colour 0 to 7 red component definition red colour component for foreground colour 0 to 7 144, 147, 150, 153, 156, 159, 162 and 165 wd7tod0 name subaddress r/w data
1999 may 11 40 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e f oreground colour 0 to 7 green component definition green colour component for foreground colour 0 to 7 145, 148, 151, 154, 157, 160, 163 and 166 wd7tod0 f oreground colour 0 to 7 blue component definition blue colour component for foreground colour 0 to 7 146, 149, 152, 155, 158, 161, 164 and 167 wd7tod0 b ackground colour 0 to 7 red component definition red colour component for background colour 0 to 7 168, 171, 174, 177, 180, 183, 186 and 189 wd7tod0 b ackground colour 0 to 7 green component definition green colour component for background colour 0 to 7 169, 172, 175, 178, 181, 184, 187 and 190 wd7tod0 b ackground colour 0 to 7 blue component definition blue colour component for background colour 0 to 7 170, 173, 176, 179, 182, 185, 188 and 191 wd7tod0 f oreground transparent colour definition foreground colour transparency 192 w d7 to d0 foreground colour is not transparent logic 0 foreground colour is transparent logic 1 f oreground alpha blending colour definition foreground colour alpha blending 193 w d7 to d0 foreground colour is not alpha blendable logic 0 foreground colour is alpha blendable logic 1 b ackground transparent colour definition background colour transparency 194 w d7 to d0 background colour is not transparent logic 0 background colour is transparent logic 1 b ackground alpha blending colour definition background colour alpha blending 195 w d7 to d0 background colour is not alpha blendable logic 0 background colour is alpha blendable logic 1 name subaddress r/w data
1999 may 11 41 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e on screen display window c ursor position 1 cursor row 196 w d5 to d0 c ursor position 2 cursor column 197 w d5 to d0 c haracter appearance foreground colour code 198 w d2 to d0 background colour code d5 to d3 character appearance d7 and d6 picture information will be overwritten by osd data d7 = 0 and d6 = 0 transparency of osd transparent colours d7 = 0 and d6 = 1 1 : 1 alpha blending of osd alpha colours d7 = 1 and d6 = 0 1 : 2 alpha blending of osd alpha colours d7 = 1 and d6 = 1 c haracter code code of character to be placed at cursor position 199 w d6 to d0 on screen display character matrix c haracter code code of character to be de?ned 200 w d6 to d0 c haracter pattern character de?nition pattern 201 w d7 to d0 tft display interface g eneral configuration 1 output width 202 w d0 double pixel output (48 bits) logic 0 single pixel output (24 bits) logic 1 output clock polarity d1 data output with respect to falling edge of pin pclk logic 0 data output with respect to rising edge of pin pclk logic 1 data quali?er polarity d2 active low pin pde logic 0 active high pin pde logic 1 horizontal sync polarity d3 active low horizontal sync at pin phs logic 0 active high horizontal sync at pin phs logic 1 vertical sync polarity d4 active low vertical sync at pin pvs logic 0 active high vertical sync at pin pvs logic 1 name subaddress r/w data
1999 may 11 42 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e g eneral configuration 2 line length controlling in active video region 203 w d0 line length controlling disabled logic 0 line length controlling enabled logic 1 line length controlling in border region d1 line length controlling disabled logic 0 line length controlling enabled logic 1 line length controlling in top blanking region d2 line length controlling disabled logic 0 line length controlling enabled logic 1 output interface mode d3 free running output interface timing (external sdram required) logic 0 synchronous output interface timing (without external sdram) logic 1 blanking mode d4 normal operating mode logic 0 all data outputs are at low level (black colour) logic 1 output interface enabling d5 output interface disabled, no data processing logic 0 output interface enabled, normal data processing logic 1 data quali?er generation mode d6 disable pulse generation at pin pde during vertical syncs logic 0 enable pulse generation at pin pde during vertical syncs logic 1 line synchronization d7 normal mode logic 0 do not use logic 1 h orizontal line length in blanking region horizontal line length in blanking region 204 and 205 w d10 to d0 h orizontal line length in border region horizontal line length in border region 206 and 207 w d10 to d0 h orizontal line length in active video region horizontal line length in active video region 208 and 209 w d10 to d0 v ertical frame end vertical frame length 210 and 211 w d10 to d0 v ertical border region start vertical start of border region 212 and 213 w d10 to d0 v ertical active video region start vertical start of active video region 214 and 215 w d10 to d0 h orizontal delay of start of vertical sync horizontal start delay of vertical sync pulse at pin pvs 216 and 217 w d10 to d0 name subaddress r/w data
1999 may 11 43 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e h orizontal delay of end of vertical sync horizontal end delay of vertical sync pulse at pin pvs 218 and 219 w d10 to d0 h orizontal sync pulse start start of horizontal sync pulse at pin phs 220 and 221 w d10 to d0 h orizontal sync pulse end end of horizontal sync pulse at pin phs 222 and 223 w d10 to d0 d ata qualifier start start of border region and horizontal data quali?er at pin pde 224 and 225 w d10 to d0 d ata qualifier end end of border region and horizontal data quali?er at pin pde 226 and 227 w d10 to d0 h orizontal active region start start of horizontal active video region 228 and 229 w d10 to d0 v ertical sync pulse end vertical sync pulse end at pin pvs 230 and 231 w d10 to d0 m aximum horizontal line length maximum reachable line length for length controlling 232 and 233 w d10 to d0 name subaddress r/w data 8.2 clock management 8.2.1 c lock generation and multiplexing for normal operation the SAA6721e uses two clock inputs; pin vclk and pin clk. vclk is used as the sample clock provided by the external adcs or decoder. the frequency and the sample edges of this clock depend on the number of adcs connected, or on the video dot clock: 1 adc mode: maximum vclk frequency is 150 mhz 2 adc mode: maximum vclk frequency is 75 mhz. the clock from pin clk is used as an internal reference, and it is the source clock for the internal pll. the memory clock mclko and panel clock pclk are derived from the pll (see fig.11): where n = pre-divider ratio, m = post-divider ratio and mclko clk n ----------- 16 = pclk clk n ----------- 32 m ------ = 5 mhz clk n ----------- 8mhz it is possible to drive the memory clock output directly without the internal pll via pin mclki. to achieve this the programming flag pll_mclk must be set to logic 0. the same is possible for the panel output clock. therefore the system clock clk is used directly. the system clock is controlled by pll_pclk which must be set to logic 0.
1999 may 11 44 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.2.2 c lock divider the pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval from 1.5 to 10.5. all further dividing ratios are in steps of 1.0; see fig.12 and table 9. programming of the clock dividers must be done using the registers 26 to 32. it is necessary that the clock dividers must be disabled before programming and be enabled afterwards. this can be done with pre_div_enable and post_div_enable. table 9 clock divider programming ratio p-counter (hex) n-counter (hex) n-offset counter (hex) half clk 1.5 10 10 1 1 2.0 00 00 0 0 2.5 30 30 2 1 3.0 10 10 0 1 3.5 41 41 3 1 fig.11 clock generator. handbook, full pagewidth mhb251 pll 32 pre-divider post-divider ? 2 mclko pclk mclki clk fig.12 clock waveforms. handbook, full pagewidth mhb252 clk clk/4 clk/5 clk/4.5 clk/5.5
1999 may 11 45 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 4.0 11 00 0 0 4.5 61 61 4 1 5.0 21 21 0 1 5.5 72 72 5 1 6.0 22 00 0 0 6.5 92 92 6 1 7.0 32 32 0 1 7.5 a3 a3 7 1 8.0 33 00 0 0 8.5 c3 c3 8 1 9.0 43 43 0 1 9.5 d4 d4 9 1 10.0 44 00 0 0 10.5 f4 f4 a 1 11.0 54 54 0 1 12.0 55 00 0 0 13.0 65 65 0 1 14.0 66 00 0 0 15.0 76 76 0 1 16.0 77 00 0 0 17.0 87 87 0 1 18.0 88 00 0 0 19.0 98 98 0 1 20.0 99 00 0 0 21.0 a9 a9 0 1 22.0 aa 00 0 0 23.0 ba ba 0 1 24.0 bb 00 0 0 25.0 cb cb 0 1 26.0 cc 00 0 0 27.0 dc dc 0 1 28.0 dd 00 0 0 29.0 ed ed 0 1 30.0 ee 00 0 0 31.0 fe fe 0 1 32.0 ff 00 0 0 ratio p-counter (hex) n-counter (hex) n-offset counter (hex) half clk
1999 may 11 46 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.3 rgb/yuv input interface 8.3.1 s ampling mode the input interface allows sampling of rgb or yuv data. because of that two different modes must be supported: rgb data sampling and yuv data sampling. the flag rgb_proc_on selects rgb mode sampling if asserted. if the flag is not asserted yuv data is selected. sampling of interlaced rgb data is enabled by rgb_interl_on. 8.3.2 rgb data sampling sampling is done on the rising edge or on both edges of vclk depending on the number of adcs. the sample window is defined by v_offset, h_offset, v_length, and h_length. the offset counters start counting from the second edge of their reference signals, i.e. vvs for vertical offset and vhs for horizontal offset. figure 13 shows the horizontal offset. the polarities of the sync signals are given with vs_pol and hs_pol. the vertical sample offset is given in lines and the horizontal offset is measured in pixels. the width of the sample window is defined by the length counters. the vertical width is measured in lines and the horizontal width in pixels, but only even pixel numbers are allowed. the sample clock for the adcs is always vclk, but in dual adc mode this clock is half the pixel clock. because of that, in dual adc mode, both clock edges are used to sample data by the adcs. table 10 clock relationships in single adc mode, with each vclk clock, a pixel must be sampled from port a. in dual adc mode, at each vclk clock edge, a pixel must be sampled alternating from port a or b. the flag adc_sample_seq selects from which port data sampling starts after the active edge of the horizontal synchronization pulse. 8.3.3 c lamp pulse generation the clamp pulse is generated with respect to half the dot clock. the counters values responsible for switching the clamp pulse on or off are clamp_on and clamp_off. both start counting from the second edge of vhs. the polarity of clamp is given with clamp_pol. number of adcs vclk vclk sample edge 1 dot clock positive 2 1 2 dot clock both fig.13 rgb data sampling. handbook, full pagewidth mhb253 vhs rgb data h_offset h_length 0 1 2 3 4 5 n
1999 may 11 47 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.3.4 g ain correction pulse generation the gainc signal is the delayed horizontal sync pulse (vhs). it is delayed with respect to half the dot clock. the first edge of vhs is delayed by gainc_on_delay and the second edge by gainc_off_delay (see fig.14). the polarity is programmed by gainc_pol. fig.14 gain adjustment and clamp pulse generation. handbook, full pagewidth mhb254 vhs rgb data gainc clamp gainc_off_delay gainc_on_delay clamp_on clamp_off 8.3.5 yuv data sampling in yuv mode the input interface receives digital yuv encoded video data from an external video decoder. the video data can be in 4 : 4 : 4, 4 : 2 : 2, 4 : 1 : 1, or yuv 4:2:2 with ccir 656 codes. for the 4 : 4 : 4, 4:2:2, and 4:1:1 formats the reference signals vvs and vhs must be considered to identify the frames. the polarity of these signals is programmable with vs_pol and hs_pol. the region of valid video data and the start point for the uv sequence is defined by href applied at pin vpd6. external reference signals are needed for sampling the yuv 4:4:4, 4:2:2 and 4 :1:1 data. if ccir 656 data is to be sampled, all external reference signals are ignored, because their information is coded into the data stream. all information about active video, blanking and field id is taken from the ccir 656 codes. the selection of the input format is done by yuv_input_mode as shown in table 11. table 11 yuv input modes data sampling occurs in relation to horizontal and vertical offset counters, and horizontal and vertical length counters. they are the same as for programming the rgb input, v_offset, h_offset, v_length, and h_length. all offset and length values are relative to the whole frame, and not to odd or even fields (see fig.15). yuv_input_mode[1 and 0] description 0 yuv 4:2:2 with ccir 656 codes 1 yuv 4:1:1 2 yuv 4:2:2 3 yuv 4:4:4
1999 may 11 48 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e fig.15 line sampling. handbook, full pagewidth mhb255 odd line even line line number 1 314 2 315 324 12 325 3 316 4 10 323 11 317 5 318 321 9 322 6 319 7 8 320 vsync end offset 8 9 10 5 6 7 2 3 4 1 0 8.3.5.1 field capturing another problem that must be considered is frame dropping. it is possible that the connected video source only provides either odd or even frames, or that the video source drops frames. therefore the input interface must process the incoming video stream in several ways, as shown in table 12. table 12 field capture modes yuv_?eld_mode[1 and 0] description 0 all incoming frames are captured 1 after an odd frame the next even frame will be captured, and vice versa 2 capture only odd frames 3 capture only even frames 8.3.5.2 yuv clocking vclk, or alternatively the clock from mclki, is used for clocking the input interface in yuv mode and the data path behind the external clock. this second port will be used if yuv_clk_mux is set to logic 1. the external clock is the line-locked video clock from the video decoder. this clock is gated by cref and applied at pin vpd7. data is only to be sampled if this signal is asserted. alternatively the line-locked video clock divided by two can be used (if provided by the decoder). in this event cref must be tied to logic 1 or logic 0 depending on its programmed polarity.
1999 may 11 49 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.4 video mode and synchronization signal detection the SAA6721e can be used to build up multi-sync systems using an external microcontroller. therefore information about the input resolution and timing are provided (see tables 7 and 8). the flags pos_vsync and pos_hsync show the polarity of the synchronization signals at vvs and vhs. if they are set to logic 1 they are active high, and their active edge is the falling edge. if these flags are set to logic 0, they are active low. for detecting video electronic standard association (vesa) power-down modes or a not connected input, the presence of the synchronization signals will be detected: it can be read via no_vsync, and no_hsync. these flags are active high. the timing of the applied rgb video input can be taken from v_lines reporting the number of lines of a full frame. the horizontal timing can be calculated from h_clocks. this register shows the length of a line in numbers of reference clock periods. the reference clock is equal to the panel clock pclk in double pixel output mode (48 bits in parallel), or it is half the panel clock pclk in single pixel output mode (24 bits in parallel). if one of the above mentioned flags or counters changes its value, it can be assumed that a new graphics mode has been applied. in this case an interrupt at pin int will be generated. this port is active low. the reset can be cleared by writing a logic 1 to intr_clear at address 24. for adjusting the rgb input interface to a new graphics mode, the registers of the section rgb auto adjustment are to be used. with this auto adjustment support it is possible to measure the number of blanking pixels and lines between the end of the synchronization pulses and the active video. the horizontal and vertical back porch blanking can be read out at black_pixels and black_lines. the number of active pixels or lines will be reported from non_black_pixels and non_black_lines. the first value should be used for tuning the sample clocks pll so that this value corresponds to the number of pixels to be sampled horizontally in this specific graphics mode. to distinguish between blanking and active video ref_colour is used. if the sample values of all three colour components are below this value the pixel is treated as a blanking pixel, otherwise it is treated as active video. additionally a reference pixel can be defined with ref_line and ref_pixel. the r, g, and b components of this pixel are sampled and available at ref_pixel_red, ref_pixel_green, and ref_pixel_blue. they can be used for fine tuning the external pll in frequency and phase and for colour gain adjustment. 8.5 memory interface and de-interlacer unit the SAA6721e features a 64 bits wide synchronous dram interface. both sdram and sgram devices can be used. there is no difference in programming when using sdram or sgram devices. the only thing that must be considered is the amount of frame buffer memory, which must be enough for the specific application. depending on the kind of input data stream the memory interface must be switched to yuv 4 : 2 : 2 or yu v4:1:1 mode by setting yuv422_mode to logic 1 to enable 16 bits per pixel processing. if this flag is set to logic 0, 24 bits per pixel are used which is needed for rgb and yuv 4 : 4 : 4 processing. if not the whole bandwidth of the 64 bits wide data bus is needed, the data bus can be downsized to 48 or 32 bits. this is done with the parameter data_width, see table 13. table 13 data bus width since the different timing parameters of various ram device types are different, all important timing values are programmable and must be set-up according to the used ram types. to reach a high effective bandwidth all access to the external memory is organized in bursts. the larger the number of subsequent read or write accesses the higher the effective bandwidth. an effective bandwidth of 91% can be reached by doing 64 words burst accesses. the ram devices support a maximum internal burst length of 8 words only, so 8 of these bursts must be run subsequently. this can be programmed by setting up the ram with sdram_burst_length_code taken from the specification data of the sdram or sgram. the memory interface must be programmed to 64 words bursts by programming the ram burst length sdram_burst_length to 8, and the number of these bursts in burst_seq_length to 8. the internal structure of the SAA6721e is optimized for 64 words bursts. data_width[1 and 0] programmed bus width (bits) 032 148 264
1999 may 11 50 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.5.1 m emory interface limitations the timing parameters of the memory access can be programmed to fulfil the timing restrictions of several sdram or sgram devices. but there are some limitations, as shown in table 14. table 14 memory interface limitations 8.5.2 i nitialization of external memory all sgram and sdram devices must be powered-up and initialized correctly. the SAA6721e memory interface is implemented to fulfil the intel pc100 sdram specification. table 15 shows the required programming steps to initialize the memory correctly. table 15 memory initialization programming 8.5.3 f rame and field memory the memory interface acts as a decoupling unit to adapt the different frame rates at the video input to the panel output. the external memory is also used for the de-interlacing unit which reconstructs the frames from odd and even fields in interlaced mode. the algorithm of de-interlacing can be selected by deint_mode (see table 16). timing symbol parameter conditions minimum value (clock periods) cas latency column address strobe (cas) latency 3 2 t rcd activate to command delay; row address strobe (ras) to cas delay 3 2 t rrd ras to ras bank activity delay t rrd 1 t rcd ; proposal is t rrd =t rcd +1 3 3 t rp ras precharge time 3 3 t wr write recovery time 3 1 t rc ras cycle time 3 3 sdram_burst_length must be supported by sdram 3 2 burst_seq_length must be an even number 3 2 t rsc register set cycle (rsc) mode time internally de?ned; cannot be changed =8 step action registers 1 SAA6721e power-on reset - 2 set-up timing parameters 51 to 55 3 start memory initialization with setting memory_init 24 4 set-up all other parameters 50 to 74 5 release internal memory reset together with other internal resets 24
1999 may 11 51 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e table 16 de-interlacing modes de-interlacing mode 0 must be selected for non-interlaced input of rgb or yuv. only one memory area is needed, whose start address must be programmed into field1_row and field1_column. normally this should be logic 0 for both values. all other modes need more than one memory area. so the other field start addresses must be programmed (see fig.16). the memory interface addresses alternately the two banks of the sdram or sgram devices. so the memory needs for the field stores must be calculated from the following formula: , where number_of_pixels depends on the input resolution and whether it is an odd or even field bytes_per_pixel is 2 for yuv 4:2:2 and yuv 4:1:1; 3 for yuv 4:4:4 and rgb. all memory addresses must be transformed into row and column addresses used by drams. the column address is formed by the 8 lsbs (field_memory_size[7 to 0]), and the row address by all the other address bits (field_memory_size[18 to 8]). the column address must be aligned to the number of internal dram bursts, normally in steps of 8 (0, 8, 16, etc.). deint_mode[1 and 0] algorithm memory needs 0 no de-interlacing and no ?ltering 1 frame buffer 1 de-interlacing without ?ltering 2 ?eld buffers 2 de-interlacing with spatial ?ltering 2 ?eld buffers 3 de-interlacing with temporal ?ltering 4 ?eld buffers fig.16 memory usage for de-interlacing. handbook, full pagewidth mhb256 deint_mode 0 ?ld1_row/column ?ld1_row/column ?ld2_row/column deint_mode 1/2 ?ld1_row/column ?ld2_row/column deint_mode 3 ?ld3_row/column ?ld4_row/column odd field even field odd field odd field even field even field field_memory_size[18 to 0] number_of_pixels bytes_per_pixel 2 data_bus_width (bytes) ----------------------------------------------------------------------- =
1999 may 11 52 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e the values given in table 17 can be used for frame resolutions up to 720 576 pixels which complies to the 625 line/50 hz mode. table 17 field start address values 8.5.4 f rame recovery during de-interlacing and also in mode 0, output frames with the right vertical and horizontal dimensions must be generated. since size information is not stored in the external memory, the output frame resolution must be programmed into the registers frame_length and line_length. the first value gives the vertical resolution, and the second the horizontal resolution in pixels. if no downscaler is used, these values can be taken directly from the input interface. if downscaling is activated, the size of the de-interlacer output frame must be calculated from the rgb input frame size divided by the downscaling factors. if no valid data stream is applied at the rgb/yuv input interface, the de-interlacer is able to generate a picture by itself. this will be enabled with blank_screen at address 25. the colour of this frame is defined by blank_colour_red, blank_colour_green, and blank_colour_blue. 8.6 scaling two different scaling units are implemented to perform both up and downscaling. the downscaling engine, which is located before the memory interface, and the upscaling engine after the memory interface. 8.6.1 d ownscaling if the downscaler is to be used, it must be enabled by setting flags down_v_scaler_on and down_h_scaler_on. for vertical scaling a line memory buffer is needed. this memory must be switched to downscaling mode by setting down_v_scaler_mem to logic 1 because only one is available. field value (hex) field1 row/column 000/0 field2 row/column 08d/0 field3 row/column 100/0 field4 row/column 180/0 setting up the desired downscaling ratios is achieved by programming the scaling increments down_v_incr, down_v_corr, and down_h_incr, down_h_corr. this must be done for both vertical and horizontal scaling. where xx is equivalent to down_v_incr or down_h_incr and yy is the fraction of the result in 1 100 . this is the value for programming the increment correction values down_v_corr and down_h_corr. example: sxga ? xga horizontal: this means down_h_incr = 51 and down_h_corr = 20. vertical: this means down_v_incr = 48 and down_v_corr = 0. 8.6.2 u pscaling the upscaler must be activated by up_v_scaler_on and up_h_scaler_on. to use the line memory for upscaling, down_v_scaler_mem must be set to logic 0. to set-up the zoom factor, the scaling increments up_v_incr, up_v_corr, up_h_incr, and up_h_corr must be programmed. where xx is equivalent to up_v_incr or up_h_incr and yy is the fraction of the result in 1 100 . this is the value for programming the increment correction values up_v_corr and up_h_corr. example: xga ? sxga horizontal: this means up_h_incr = 80 and up_h_corr = 0. vertical: this means up_v_incr = 85 and up_v_corr = 33. incr number_of_output_pixels number_of_input_pixels ------------------------------------------------------------------ - 64 xx.yy = = 1024 1280 ------------ - 64 51.20 = 768 1024 ------------ - 64 48.00 = incr number_of_output_pixels number_of_input_pixels ------------------------------------------------------------------ - 64 xx.yy = = 1280 1024 ------------ - 64 80.00 = 1024 768 ------------ - 64 85.33 =
1999 may 11 53 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.6.3 u pscaler transition function a special feature of the zooming algorithm is a free programmable transition function which allows smoothing or sharpening of the transition between pixels that have been calculated. this function will be stored in a look-up table, containing 64 words of 7 bits; thus a function of 64 points with a resolution from 0 to 64 can be programmed. programming is performed using the registers coeff_index and coeff_value. the first register defines the point of the function, the second the value. writing to register coeff_value increments the value of coeff_index automatically, so that the next point of the function is addressed. additionally no register increment will be performed, so that subsequent i 2 c-bus write addresses always have the same register coeff_value. 8.7 panning unit if the scaled or non-scaled input frame does not fit into the needed output frame, whether it is to large or to small, the panning unit enlarges the input frame to the size of the output frame. this is achieved by generating a border region around the input frame, or it cuts the input frame down to the size of the output frame. the position of the top left pixel of the input frame inside the output frame must be defined with pic_v_offset and pic_h_offset. the output frame size must be programmed with out_v_size and out_h_size (see fig.17). if the input frame is to large only the right and bottom part will be cropped. the colour of the generated border region must be set via border_colour_red, border_colour_green, and border_colour_blue. fig.17 picture positioning. handbook, full pagewidth mhb257 input frame output frame pic_h_offset pic_h_offset pic_v_offset pic_v_offset out_v_size out_h_size
1999 may 11 54 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.8 overlay port 8.8.1 o verlay insertion if ovl_syncs_active is high, the vertical and horizontal sync signals for the external osd controller are generated. the flag ovl_insert_active switches on the insertion of the information at the overlay port provided by an external osd controller into the data stream at the position defined by ovl_v_offset, ovl_hs_start, and ovl_hs_latency (see fig.18). the incoming data from ports ovl0 and ovl1 is replaced by the defined colour information and treated as a double pixel, which will be inserted into the data stream if ovact is set. the pixel at port 0 is then the left pixel, and the pixel at port 1 is the right pixel. the sampling of the ports ovl0 and ovl1 is done on the positive edge of ovclk in the event that sample_edge is asserted, otherwise on the falling edge of ovclk. fig.18 overlay window positioning. handbook, full pagewidth mhb258 output frame overlay window ovl_v_offset ovl_hs_start ovl_hs_latency ovl_h_length ovl_v_length ovl_vs_start one line vsync
1999 may 11 55 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.8.2 s ync generation the start of the horizontal sync pulse is defined in ovl_hs_start and the polarity in ovl_hs_pol. the sync pulse length is defined in ovl_hs_length (see fig.19). it is possible to generate a hsync pulse from one clock cycle length up to longer than the horizontal overlay data. the vertical sync pulse starts at ovl_vs_start and is always one output frame line long. 8.8.3 d ata sampling data sampling from the two ports ova and ovb starts from the beginning of the horizontal sync pulse, but the number of clocks defined in ovl_hs_latency will decide when reading data from the overlay port will start (see fig.19). the end of the sync pulse is not important. fig.19 hsync generation and data sampling (hsync latency = 2). handbook, full pagewidth mhb259 o0 o2 o4 o6 o8 o1 o3 o5 o7 o9 ovclk ovhs ova ovb ovl_hs_start ovl_hs_length ovl_hs_latency ovl_h_length ovact 8.8.4 ovclk gating all of the above mentioned functions will only work during internal processing of valid video data, and not during internal blanking regions. this can give problems if the overlay window is displayed at the left border of the picture because the first pixels of a line will be processed due to the internal pipeline structure. to overcome this, the ovclk can be gated to disable data processing by the external osd controller during internal blanking. clock gating is enabled by clk_gating_on. 8.9 colour space matrix the back-end processing of the SAA6721e and the tft panels require rgb video data. so the built-in colour space matrix is used to convert video data from yuv space into rgb space. it can be enabled by setting csm_bypass to logic 0 (see general configuration section of the programming register table 7), otherwise the colour space converter will be bypassed. 8.10 colour correction the colour correction unit can be used to perform gamma correction, change of brightness, and so on. this can be achieved by means of a look-up table. each colour component value in an rgb pixel is used as a pointer into this table. the value from the table will replace the incoming colour. various tables exist for r, g, and b components. programming of a table must be performed using the programming registers 47 to 49 (see the colour correction section of the programming register table 7). it must be decided which component table should be written to (red_prog, green_prog, blue_prog). in colour_index the start address or the first incoming colour value for programming must be written. then subsequent writing to colour_value fill the table. at this address the i 2 c-bus address auto-increment stops, but the value programmed into colour_index will be incremented. it is possible to write to more than one table by enabling of programming multiple colour components.
1999 may 11 56 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e if the colour correction unit is switched to bypass mode (when colour_correction_on is not asserted), the incoming colours are used for further processing. writing to the colour correction table is possible during data processing. 8.11 on screen display 8.11.1 osd generals the implemented osd is a character based window system. it consists of a character matrix memory where all character definitions are stored, and an osd window memory defining the osd windows contents. the osd window will be inserted into the video data stream if osd_active is set to logic 1. writing to these memories can be done during data processing. 8.11.2 osd window the osd window contains the character, colour and appearance information to be displayed. such a definition exists for each character position. a character can use one of 8 different foreground and background colours. some of these colours can be defined as transparent colours where the original picture information will be displayed instead, as alpha blended colours where a 1 : 1 or 1 : 2 alpha blending will be done between picture and osd, or as normal colours. transparency or alpha blending effects will be enabled or disabled for the single characters. the size and outline of the visible osd window can be programmed as long as the internal memory meets the needs. this memory is able to store information of 1152 characters information. the programming registers osd_v_size and osd_h_size define the osd window size in characters. the window position inside the output frame must be defined with osd_v_offset and osd_h_offset (see fig.20). the osd can be programmed to use a 24 24 character matrix, or a 12 16 matrix. the first one should be used for kanji and the second for standard characters. the selection of the font size is done by char_size. a logic 1 selects 24 24 font, and a logic 0 the smaller 12 16 font. if the small 12 16 font is used, up to 128 different characters can be defined. alternatively up to 42 characters of the larger 24 24 font can be used. table 18 gives some possible osd settings. fig.20 osd window positioning. mhb260 handbook, halfpage output frame osd osd_h_offset osd_v_offset osd_v_size osd_h_size
1999 may 11 57 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e table 18 osd window size the whole osd window can be zoomed in both directions by a factor of two by setting zoom2 to logic 1. this results in pixel doubling horizontally and vertically. each character can be displayed using 1 of 8 different foreground and background colours. these sixteen colours can be chosen from the full true colour palette with 8 bits per colour component. the definition of these colours is in registers 144 to 191 (see osd section of the programming register table 7). the first 8 colour entries are used for foreground colours, and the second half is used for defining the background colours. registers 192 to 195 (see table 7) decide the transparency and alpha blending effects. if one of these effects is enabled for a specific character, only the colours defined as transparency or alpha blending colours will be used to generate these effects. each character information in the osd window memory consists of 15 bits of information. this is given in tables 19 and 20. table 19 character appearance de?nition the character code is used to address the defined characters inside the matrix memory. the appearance bits decide about transparency and alpha blending, and background and foreground colour are indices to the colour definition registers. osd size osd window resolution/pixels 24 24 12 16 32 16 768 384 384 256 40 20 960 480 480 320 48 24 1152 576 576 384 character information number of bits character code 7 appearance 2 background colour 3 foreground colour 3 table 20 colour effects to access a certain character position its coordinates must be programmed into registers 196 (cursor_row) and 197 (cursor_column), see table 7. after that, the colours and appearance of the character must be defined in address 198 (see table 7). this definition is valid for all further writes to register 199 (char_code), see table 7. after writing to this register the cursor position changes to the next right position. at line end it wraps around to the first left character in the line below. i 2 c-bus auto-increment is not active at register 199 (see table 7), so that subsequent i 2 c-bus byte write accesses will define several characters. 8.11.3 osd character matrix two different font sizes are supported; 24 24 and 12 16 pixels. with the internal matrix memory 42 characters (24 24 pixels) can be defined, or 128 characters (16 12 pixels). the definition of the characters is achieved by writing to registers 200 and 201 (see table 7). the first register must be written to with the character code of the character to be defined. then the bytes with the pixel pattern must be written to address 201 (see table 7). the definition of a character is done with 3 bytes per line at 24 24 font (72 bytes per character), and with 3 bytes per 2 lines at 12 16 font (24 bytes per character), see fig.21. appearance value effect 0 osd character colours are displayed instead of the picture colours 1 osd character colours de?ned as transparency colours will be replaced by the picture colours 2 osd character colours de?ned as alpha blending colours will be alpha blended 1 : 1 with the picture colours 3 osd character colours de?ned as alpha blending colours will be alpha blended 2 : 1 with the picture colours
1999 may 11 58 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.12 temporal dithering (frame rate controller) the SAA6721e is able to display true colour (8 bits per colour) on high colour displays (6 bits per colour). the algorithm used is temporal dithering. this feature can be enabled by setting frc_on to logic 1 in the general configuration register block (see table 7). 8.13 output interface 8.13.1 g eneral the output interface is the interface between the SAA6721e and the tft panel. its timing parameters can be programmed in a wide range to support panels of many different manufacturers. the output interface can operate in two different modes. the first mode is the free running mode which is adapted to the memory mode of the SAA6721e. in this mode the output is independent from the input at the rgb/yuv input interface. so the output frame generation can start directly after releasing the internal reset. for getting a high frame rate the output timing can be programmed to satisfy the minimum timing requirements of the panel. fig.21 character matrix organization. mhb261 handbook, halfpage 1 byte (a) (b) a: 24 24 font definition. b: 12 16 font definition. the second mode is synchronized to the input data, mainly implemented to support the SAA6721es no memory mode. in this mode the input data is sent directly to the output interface, which must synchronize its output timing to get the same frame rate as the input. additionally it starts generating vertical blanking and synchronization signals at pins pvs and phs directly after releasing the internal reset. after the programmed top blanking the output interface enlarges the last blanking line until data from the input interface reaches the output interface. because too long lines cause counter overflows in the panels, a controlling mechanism exists which changes the length of the blanking, border and active lines according to the timing requirements of the panel and the applied graphics mode. this mode can be enabled by setting the programming register sync_mode to logic 1, otherwise the first free running mode will be selected. the length controlling the blanking, border and active video region can be enabled by asserting blank_ctrl, border_ctrl, and active_ctrl. the output interface also supports a power-down mode which sets all output signals to logic 0. this will be activated by the programming flag power_down (see section general configuration table 7). for flicker free switching between different input modes, the output interface is able to set all data outputs to the panel to logic 0, resulting in a black picture. even if during programming and internal reset no synchronization pulses for the panel are generated and the panel loses the last picture information, the panel still displays black colour, because this is its idle state. to switch the output interface into this mode blank_tft must be set. to enable the panel interface it must be enabled with out_if_enable. the interface supports single pixel (24 bits) and double pixel (48 bits) output in parallel. the selection between these two modes must be done with single_pixel_output. the active clock edge at pclk can also be selected by clk_pol.
1999 may 11 59 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.13.2 f rame generation the output frame contains three main regions: blanking region border region active video region. the blanking region contains all front and back porch as well as the synchronization intervals. the border region is visible on the panel and is used for positioning the active video region inside this visible area. to ensure a great flexibility in the sync to input mode there are 3 different horizontal length counters (h_len_blank, h_len_border, h_len_active) with independent length control (see fig.22). a maximum value must be programmed in h_max_len which is the upper limit for line lengthening during activated control mechanism. in free running mode all 3 counters should be programmed with the same minimum values. if no border is needed, because the active video region covers the visible area of the panel, the active video length counters should point to the same positions as the border length counters. then the active video length counters have a higher priority. the border colour inserted by the output interface is the same as the blank colour in the memory interface; blank_colour_red, blank_colour_green, blank_colour_blue. fig.22 output frame and timing. handbook, full pagewidth mhb262 active video border blanking phs pvs starting point h_de_start h_active_start h_de_end h_len_blank h_hs_end h_hs_start v_vs_end v_start v_end v_active h_len_border h_len_active h_max_len
1999 may 11 60 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 8.13.3 t iming reference signals the SAA6721e supports three timing reference signals to drive the panels: pvs (vertical synchronization pulse), phs (horizontal synchronization pulse) and pde (data qualifier). the polarity of these signals is programmable. to program high polarity the three programming registers (vsync_pol, hsync_pol, de_pol) must be set to logic 1. sometimes panels require that no data qualifier signals must be active during vertical synchronization. the generation of pde pulses during active pvs can be switched off by de-asserting sync_de_inact. the position and length of the horizontal synchronization pulses in an output line must be programmed with h_hs_start and h_hs_end. the vertical synchronization pulse starts at line 0 and ends at v_vs_end. the horizontal start offset in line 0 can be set-up with h_vs_start and the horizontal end offset with h_vs_end. the data qualifier pde frames the display region that should be visible on the panel horizontally. it will be asserted at h_de_start and it will be de-asserted at h_de_end. it frames both horizontal border and active video region. 9 limiting values in accordance with the absolute maximum rating system (iec 134); all ground pins are connected together and all supply pins are connected together. note 1. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dd(pll) pll supply voltage - 0.5 +4.6 v v n voltage at digital inputs and outputs outputs in 3-state - 0.5 +5.5 v voltage at digital output outputs active - 0.5 v ddd + 0.5 v d v ss voltage difference between v ss(pll) and v ss(d) - 100 mv t stg storage temperature - 65 +150 c t amb ambient temperature 0 70 c t amb(bias) operating bias ambient temperature - 10 +70 c v es electrostatic handling voltage for all pins note 1 - 2+2kv
1999 may 11 61 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 10 characteristics v ddd = 3.0 to 3.6 v; v dd(pll) = 3.1 to 3.5 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 600 tbf ma p d digital power dissipation - 2 - w v dd(pll) pll supply voltage 3.1 3.3 3.5 v i dd(pll) pll supply current - tbf tbf ma p pll pll power dissipation - tbf - w p pll + d digital plus pll power dissipation - 2 - w digital inputs v il(scl, sda) low-level input voltage at pins sda and scl - 0.5 - +0.3v ddd v v ih(scl, sda) high-level input voltage at pins sda and scl 0.7v ddd - v ddd + 0.5 v v il(lvttl) low-level input voltage at lvttl pins - 0.5 - +0.8 v v ih(lvttl) high-level input voltage at lvttl pins 2.0 - v ddd + 0.5 v i li input leakage current -- 10 m a c i input capacitance outputs at 3-state -- 8pf input capacitance at all other inputs -- 5pf digital outputs v ol(sda) low-level output voltage at pin sda sda at 3 ma sink current -- 0.4 v sda at 6 ma sink current -- 0.6 v v ol(cmos) low-level output voltage at cmos pins -- 0.4 v v oh(cmos) high-level output voltage at cmos pins 2.4 -- v v ol(lvttl) low-level output voltage at lvttl pins -- 0.4 v v oh(lvttl) high-level output voltage at lvttl pins 0.85v ddd -- v
1999 may 11 62 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 11 timing characteristics v ddd = 3.0 to 3.6 v; v dd(pll) = 3.1 to 3.5 v; t amb =25 c; see fig.23; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit system clock input at pin clk f clk clock frequency 24 - 70 mhz d duty factor 40 50 60 % rgb/yuv sample clock input at pin vclk f vclk clock frequency single adc mode 25 - 150 mhz double adc mode 12.5 - 75 mhz d duty factor 40 50 60 % input signals at pins vvs, vhs, vpa7 to vpa0, vpb7 to vpb0, vpc7 to vpc0, vpd7 to vpd0, vpe7 to vpe0, and vpf7 to vpf0 with respect to signal at pin vclk t su set-up time - 4.0 -- ns t h hold time 7.0 -- ns output signals at pins clamp and gainc with respect to signal at pin vclk; note 1 t h hold time 8 -- ns t pd propagation delay -- 13 ns output clock to panel at pin pclk f pclk clock frequency -- 80 mhz d duty factor 40 50 60 % output signals at pins pvs, phs, pde, par7 to par0, pag7 to pag0, pab7 to pab0, pbr7 to pbr0, pbg7 to pbg0, and pbb7 to pbb0 with respect to signal at pin pclk; note 2 t h hold time pins pvs, phs and pde - 0.5 -- ns all other pins 0 -- ns t pd propagation delay pins pvs, phs and pde -- 1ns all other pins -- 3.5 ns overlay port clock output at pin ovclk f ovclk clock frequency 80 mhz d duty factor 40 50 60 % input signals at pins ovact, ova2 to ova0, and ovb2 to ovb0 with respect to signal at pin ovclk t su(i) set-up time 6.0 -- ns t h(i) hold time - 3.0 -- ns output signals at pins ovvs and ovhs with respect to signal at pin ovclk; note 1 t h(o) hold time - 1.0 -- ns t pd(o) propagation delay -- 1.0 ns
1999 may 11 63 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e notes 1. c l = 15pf, i o = 2 ma and r l =2k w . 2. c l = 15pf, i o = 4 ma and r l =2k w . 3. c l = 10pf, i o = 4 ma and r l =2k w . memory port clock output; pin mclko f mclko frequency -- 125 mhz c l load capacitance -- 20 pf d duty factor 40 50 60 % input signal at pin mclki with respect to signal at pin mclko; see fig.24 f mclki frequency -- 125 mhz d duty factor 40 50 60 % t pd propagation delay 6.5 10 ns input signals at pins dq63 to dq0 with respect to the negative edge of signal at pin mclko t su set-up time 6.0 -- ns t h hold time - 3.0 -- ns output signals at pins dq63 to dq0, ras, cas, we, a10 to a0, and ba with respect to the negative edge of signal at pin mclko; note 3 t h hold time pins dq63 to dq0 - 1 -- ns pins ras, cas, we, a10 to a0, and ba 0 -- ns t pd propagation delay pins dq63 to dq0 -- 1.0 ns pins ras, cas, we, a10 to a0, and ba -- 1.0 ns symbol parameter conditions min. typ. max. unit
1999 may 11 64 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e fig.23 data timing diagram. t su(i) : input set-up time; data input must be stable before active clock edge. t h(i) : input hold time; data input must be stable after active clock edge. t pd(o) : output propagation delay; output data becomes stable with respect to active clock edge. t h(o) : output hold time; output data stays stable with respect to active clock edge. handbook, full pagewidth 1.5 v clock input t pd(o) t h(o) data input data output data transition period data valid t h(i) t su(i) mhb490 fig.24 memory clock timing. handbook, full pagewidth 1.5 v mclki t pd mclko mhb491
1999 may 11 65 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 12 application information fig.25 test board. handbook, full pagewidth mhb263 i 2 c-bus yuv rgb rgb microcontroller p87c695 SAA6721e tda8752 tda8752 saa7113a video port vga port panel port sdram 16 mbits sdram 16 mbits sdram 16 mbits sdram 16 mbits eeprom usb
1999 may 11 66 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 13 package outline 1.27 a a 1 e 1 b a 2 a 2 a 1 unit d y ek references outline version european projection issue date 98-05-06 iec jedec eiaj mm 0.70 0.50 2.46 27.2 26.8 d 1 24.7 24.0 27.2 26.8 24.7 24.0 4.0 3.9 1.85 1.62 z d 1.84 1.04 z e 1.84 1.04 0.90 0.60 0.3 0.15 dimensions (mm are the original dimensions) sot489-1 ew 0.35 v 0 10 20 mm scale sot489-1 bga292: plastic ball grid array package; 292 balls; body 27 x 27 x 1.75 mm a max. detail x y va e e ? w b z e x z d k k e 1 d d 1 e ball a1 corner a m a b c d e f h k g j l m n p r t u v w y 2468101214161820 135791113151719
1999 may 11 67 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 14 soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 14.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 may 11 68 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 14.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 may 11 69 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e 15 definitions 16 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale 17 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 may 11 70 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e notes
1999 may 11 71 philips semiconductors preliminary speci?cation sxga rgb to tft graphics engine SAA6721e notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 64 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 02 67 52 2531, fax. +39 02 67 52 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 545004/750/01/pp72 date of release: 1999 may 11 document order number: 9397 750 04392

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